Space and process efficient MRAM and method
View Patent ↗Methods and apparatus are provided for magnetoresistive random access memory (MRAM) bits ( 52, 52 ′) combined with associated drive or sense transistors ( 53, 141 ) to form an integrated MRAM array. The MRAM array has lower electrodes ( 602, 150, 160, 162 ) of the MRAM bits ( 52, 52 ′) formed substantially directly on a source or drain region ( 56, 142, 152 - 2 ) of associated drive or sense transistors ( 53, 141 ), so that the intervening vias ( 302, 34, 36 ) and underlying interconnects layers ( 332, 35 ) of the prior art ( 20 ) can be eliminated. An interconnect layer ( 65 ) is provided above the MRAM bit ( 52, 52 ′) and transistor ( 53, 141 ) combination ( 50, 125, 129, 133 ) for coupling upper electrodes ( 41, 164 ) of the MRAM bits ( 52, 52 ′) and other electrodes ( 601, 58, 152 - 1, 152 - 3, 186 - 1, 186 - 3 ) of the transistors ( 53, 141 ) to other elements of the array. Because the lower electrodes ( 37, 602, 150, 160, 162 ) of the MRAM bits ( 52, 52 ′) are formed in substantial contact with the source or drain regions ( 56, 142 - 2, 152 - 2 ) of the transistors ( 53, 141 ), a separate interconnect layer ( 33, 35 ) and/or via ( 302, 34 ) for that purpose is not needed. As a consequence, the MRAM array is more space and process efficient.
1. A method for forming an array of magnetoresistive random access memory (MRAM) bits and associated drive or sense transistors, comprising:
forming at least one drive or sense transistor having a source or drain region;
forming a plurality of layers for at least one MRAM bit in direct contact with and overlying the at least one drive or sense transistor, including overlying the source or drain region, without an intervening via between the source or drain region and the plurality of layers, wherein the plurality of layers includes an electrode layer, a magnetically pinned layer, a barrier or spacer layer, and a magnetically free layer, and wherein the electrode layer is formed in direct contact with the source or drain region and has a width dimension that is at least as wide as width dimensions of the magnetically pinned layer, the barrier or spacer layer, and the magnetically free layer;
etching the plurality of layers to form the at least one MRAM bit; and
forming a first conductive interconnect layer above and in electrical contact with the plurality of layers for the at least one MRAM bit, with no metal layers intervening between the plurality of layers and the first conductive interconnect layer.
2. The method of claim 1 , wherein the MRAM bit has a lateral shape lying substantially within a lateral shape of the source or drain region with which it makes substantially direct contact.
3. The method of claim 1 , further comprising, forming a first conductive interconnect layer above and in electrical contact with the at least one MRAM bit.
4. The method of claim 3 , wherein the first conductive interconnect layer has spaced-apart portions, a first portion coupled to the transistor and a second portion coupled to the MRAM bit.
5. The method of claim 1 , wherein the step of forming the at least one MRAM bit comprises, forming an antiferromagnetic layer electrically coupled to the electrode layer, forming the magnetically pinned layer on the antiferromagnetic layer, forming the barrier or spacer layer on the magnetic pinned layer, and forming the magnetic free layer on the spacer or barrier layer.
6. The method of claim 5 , wherein the step of forming the at least one MRAM bit further comprises, forming an upper non-magnetic cap electrode in electrical contact with the magnetic free layer.
7. The method of claim 6 , further comprising, forming a first overlying conductive interconnect layer electrically connected to the non-magnetic cap electrode.
8. A method for forming an array of magnetoresistive random access memory (MRAM) bits and associated drive or sense transistors, comprising:
forming at least one drive or sense transistor having a source or drain region;
forming a non-magnetic contact electrode layer of at least one MRAM bit overlying and in direct contact with the at least one drive or sense transistor, including overlying the source or drain region, and without an intervening via between the source or drain region and the at least one drive or sense transistor;
forming a plurality of additional layers of the at least one MRAM bit in direct contact with non-magnetic contact electrode layer, wherein the plurality of additional layers includes a magnetically pinned layer, a barrier or spacer layer, and a magnetically free layer, and wherein the electrode layer has a width dimension that is at least as wide as width dimensions of the magnetically pinned layer, the barrier or spacer layer, and the magnetically free layer;
etching the plurality of layers to form the at least one MRAM bit;
forming a first conductive interconnect layer above and in electrical contact with the plurality of additional layers for the at least one MRAM bit, with no metal layers intervening between the plurality of additional layers and the first conductive interconnect layer.
9. The method of claim 8 , wherein the MRAM bit has a lateral shape lying substantially within a lateral shape of the source or drain region.
10. The method of claim 8 , further comprising, forming a via above and in electrical contact with the at least one MRAM bit and the first conductive interconnect layer.
11. The method of claim 8 , wherein the step of forming the at least one MRAM bit comprises, forming an antiferromagnetic layer electrically coupled to the non-magnetic contact electrode layer without a via, forming the magnetically pinned layer on the antiferromagnetic layer, forming the barrier or spacer layer on the magnetic pinned layer, and forming the magnetic free layer on the spacer or barrier layer.
12. The method of claim 11 , wherein the step of forming the at least one MRAM bit further comprises, forming an upper non-magnetic cap electrode in electrical contact with the magnetic free layer.