Reference cell layout with enhanced RTN immunity
View Patent ↗A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells.
1. A reference cell layout comprising:
a plurality of active areas in parallel to each other;
a first gate capacitively coupled to the active areas, wherein the first gate has at least one dimension greater than a corresponding dimension of a second gate of a corresponding memory cell; and
a first contact shorting the active areas to each other.
2. The reference cell layout of claim 1 wherein the first gate has a length that provides the reference cell layout with a reading gain that matches a reading gain of a corresponding memory cell.
3. The reference cell layout of claim 2 wherein the first contact has at least one dimension greater than a corresponding dimension of a second contact of a corresponding memory cell.
4. The reference cell layout of claim 3 wherein the first contact has a width equal to N times a width of the second contact, N being the number of active areas shorted by the first contact.
5. The reference cell layout of claim 1 wherein the first contact is made of metal.
6. The reference cell layout of claim 1 wherein the first gate has a length larger than a length of the second gate.
7. The reference cell layout of claim 1 wherein the active areas are substantially identical in size to active areas of corresponding memory cells.
8. The reference cell layout of claim 1 wherein the first gate has a length larger than a length of a second gate of a corresponding memory cell.
9. A memory device comprising:
a memory cell array including at least a memory cell; and
a reference cell array including at least a reference cell, the reference cell having a layout including a plurality of active areas, in parallel to each other, a first gate capacitively coupled to the active areas, and a first contact shorting the active areas to each other, wherein the first gate has a length larger than a length of a second gate of the memory cell.
10. The memory device of claim 9 wherein the first gate has a length that provides the reference cell layout with a reading gain that matches a reading gain of the memory cell.
11. The memory device of claim 10 wherein the first contact has a width equal to N times a width of a second contact of the memory cell, N being the number of active areas shorted by the first contact.
12. The memory device of claim 11 wherein the first contact is made of metal.
13. The memory device of claim 9 wherein the active areas of the reference cell are substantially identical in size to an active area of the memory cell.
14. The memory device of claim 9 wherein the reference cell has a same reading curve and program/erase performances of the memory cell, the memory device further comprising a single decoding circuit coupled to the memory cell and reference cell.
15. A memory device comprising:
a plurality of memory cells;
a reference cell layout including a plurality of active areas spaced apart from each other and a first contact shorting the active areas to each other; and
a second contact coupled to an active area of one of the memory cells, wherein the first contact has a width equal to N times a width of the second contact, N being the number of active areas shorted by the first contact.
16. The memory device of claim 15 wherein the reference cell layout has a gate having a length that provides the reference cell layout with a reading gain that matches a reading gain of one of the memory cells.
17. The memory device of claim 15 wherein the first contact is made of metal.
18. The memory device of claim 15 wherein the reference cell layout includes a first gate capacitively coupled to the active areas and the plurality of memory cells includes a plurality of active areas and a second gate capacitively coupled to the active areas of the plurality of memory cells, the first gate having a length larger than a length of the second gate.
19. The memory device of claim 15 wherein the plurality of memory cells includes a plurality of active areas spaced apart from one another, the active areas of the reference cell layout being substantially identical in size to the active areas of the plurality of memory cells.
20. The memory device of claim 15 wherein the reference cell layout has a same reading curve and program/erase performances of the plurality of memory cells, the memory device further comprising a single decoding circuit coupled to the memory cells and the reference cell layout.