Self aligned narrow storage elements for advanced memory device
A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate.
1. A method of forming a sub-lithographic charge storage element for a semiconductor structure, comprising:
providing a first layer and a second layer side-by-side on a semiconductor substrate, a portion of a side surface of the first layer being in contact with a side surface of the second layer, the first layer having a height larger than a height of the second layer, the first layer adjacent the second layer, the second layer comprising a charge-trapping material;
forming a spacer adjacent the side surface of the first layer having the portion that is in contact with the side surface of the second layer and on a portion of an upper surface of the second layer; and
removing an exposed portion of the second layer not covered by the spacer.
2. The method of claim 1 , further comprising removing the spacer.
3. The method of claim 1 , wherein the sub-lithographic charge storage element has a width of about 100 Angstroms or more and about 500 Angstroms or less.
4. The method of claim 1 , further comprising removing an upper portion of the first layer to reduce a height of the first layer.
5. The method of claim 1 , while removing an exposed portion of the second layer not covered by the spacer, an upper portion of the first layer is removed so that a height of the first layer is reduced to about 100 Angstroms or more and 1,000 Angstroms or less.
6. The method of claim 1 , wherein the sub-lithographic charge storage element comprises a nitride.
7. The method of claim 1 , wherein the sub-lithographic charge storage element comprises a silicon nitride and silicon oxide.
8. A method of making a sub-lithographic charge storage element for a memory device, comprising:
providing a first oxide layer, a nitride layer, a second oxide layer, and a first poly layer over a semiconductor substrate;
forming an opening in the first oxide layer, nitride layer, second oxide layer, and first poly layer;
forming a implanted portion through the opening in the semiconductor substrate;
forming a first layer in the opening;
removing the first poly layer;
forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the first oxide layer; and
removing an exposed portion of the second oxide layer and nitride layer not covered by the spacer.
9. The method of claim 8 further comprising removing the spacer.
10. The method of claim 8 , while removing the exposed portion of the nitride layer and first oxide layer not covered by the spacer, an upper portion of the first layer is removed so that a height of the first layer is reduced to about 100 Angstroms or more and 1000 Angstroms or less.
11. The method of claim 8 further comprising forming an oxide layer at a portion between the sub-lithographic charge storage elements.
12. The method of claim 8 further comprising forming a top oxide layer on the nitride layer after removing the exposed portion of the nitride layer and first oxide layer not covered by the spacer.
13. The method of claim 8 further comprising forming a second poly layer over the sub-lithographic charge storage element on the semiconductor substrate after removing the exposed portion of the nitride layer and first oxide layer not covered by the spacer.
14. The method of claim 8 further comprising forming an aluminum oxide layer and tantalum layer over the sub-lithographic charge storage element on the semiconductor substrate after removing the exposed portion of the nitride layer and first oxide layer not covered by the spacer.
15. The method of claim 8 , wherein the sub-lithographic charge storage element has a width of about 100 Angstroms or more and about 500 Angstroms or less.
16. The method of claim 8 , after removing the exposed portion of the second oxide layer and nitride layer not covered by the spacer, an exposed portion of the first oxide layer not covered by the spacer is removed.
17. The method of claim 1 , wherein the space is formed so that a side surface of the space is in contact with a portion of the side surface of the first layer and a bottom surface of the space is in contact with an upper surface of the second layer.
18. The method of claim 1 , wherein a height of the space is equal to a difference in the height between the first layer and the second layer.
19. The method of claim 8 , wherein the space is formed so that a side surface of the space is in contact with a portion of the side surface of the first layer and a bottom surface of the space is in contact with an upper surface of the first oxide layer.
20. The method of claim 8 , wherein a height of the space is equal to a height of the first poly layer.