Voltage regulation system
View Patent ↗A voltage regulation system is provided including detecting a feedback voltage less than a reference voltage; asserting a current source gate output by the feedback voltage less than the reference voltage; activating a gated current source by the current source gate output; and waiting a delay interval before negating the current source gate output for turning off the gated current source.
1. A method of operating a voltage regulation system comprising:
detecting a feedback voltage less than a threshold voltage;
asserting a current source gate output by the feedback voltage less than the threshold voltage;
activating a gated current source by the current source gate output; and
waiting a delay interval before negating the current source gate output for turning off the gated current source by:
activating a second delay interval transistor,
discharging a delay capacitor through the second delay interval transistor, and
detecting the delay capacitor discharged for negating the current source gate output.
2. The method as claimed in claim 1 wherein activating the gated current source includes sourcing a current from a current mirror.
3. The method as claimed in claim 1 wherein asserting the current source gate output includes:
monitoring an operational amplifier; and
activating a first delay interval transistor by the operational amplifier.
4. The method as claimed in claim 1 further comprising charging an output capacitor through the gated current source by activating the current source gate output.
5. A method of operating a voltage regulation system comprising:
detecting a feedback voltage less than a threshold voltage by monitoring an operational amplifier;
asserting a current source gate output by the feedback voltage less than the threshold voltage;
activating a gated current source by the current source gate output includes enabling a switch transistor; and
waiting a delay interval before negating the current source gate output for turning off the gated current source including charging an output capacitor by:
activating a second delay interval transistor;
discharging a delay capacitor through the second delay interval transistor includes discharging the delay capacitor through a resistor; and
detecting the delay capacitor discharged for negating the current source gate output includes sourcing the current source gate output by a hysteretic buffer.
6. The method as claimed in claim 5 wherein activating the gated current source includes sourcing a current from a current mirror having a first transistor and a second transistor in which configuring the current mirror includes establishing a current limit by a current set resistor.
7. The method as claimed in claim 5 wherein asserting the current source gate output includes:
monitoring the operational amplifier for activating a current source on signal; and
activating a first delay interval transistor by the operational amplifier including charging a delay capacitor.
8. The method as claimed in claim 5 further comprising charging an output capacitor through the gated current source by activating the current source gate output including limiting a peak voltage.
9. A voltage regulation system comprising:
an operational amplifier for detecting a feedback voltage less than a threshold voltage;
a current source gate output from the operational amplifier;
a gated current source coupled to the current source gate output; and
a delay turn-off circuit for turning off the gated current source includes:
a second delay interval transistor,
a resistor coupled to the second delay interval transistor,
a delay capacitor coupled to the resistor, and
a hysteretic buffer coupled to the resistor and the delay capacitor.
10. The system as claimed in claim 9 further comprising a current mirror, in the gated current source, configured with a first transistor and a second transistor.
11. The system as claimed in claim 9 wherein the delay turn-off circuit includes:
the operational amplifier for monitoring the feedback voltage; and
a first delay interval transistor coupled to the operational amplifier.
12. The system as claimed in claim 9 further comprising an output capacitor for storing a current from a second transistor of the gated current source.
13. The system as claimed in claim 9 further comprising:
a switch transistor in the gated current source; and
an output capacitor coupled to the gated current source for charging the output capacitor by the switch transistor activated.
14. The system as claimed in claim 13 further comprising a current mirror, in the gated current source, configured with a first gate of a first transistor coupled to the first gate of a second transistor.
15. The system as claimed in claim 13 further comprising:
a feedback resistor coupled to the output capacitor; and
a bias resistor coupled to the feedback resistor for scaling the feedback voltage from the output capacitor.
16. The system as claimed in claim 13 further comprising a current source coupled to the first gate of a first transistor and a second transistor in which the first transistor is coupled through the current source and the second transistor is coupled to a load.