Low power serial link
View Patent ↗The present invention relates to a low power serial link employing differential return-to-zero signaling. A receiver circuit consistent with some embodiments includes an input circuit for receiving differential serial data signals that form a differential return-to-zero signaling and a clock recovery circuit. The clock recovery circuit is coupled to the input circuit and includes a logic gate configured to generate a clock signal by using said differential serial data signals.
1. A receiver circuit comprising:
an input circuit for receiving differential serial data signals that form a differential return-to-zero signal, wherein said differential return-to-zero signal comprises a first signal that transmits a high bit on a first differential link and a second signal that transmits a low bit on a second differential link, wherein said first and second signals comprise duty cycles less than 50%; and
a clock recovery circuit, coupled to said input circuit, said clock recovery circuit comprising a logic gate for receiving said differential return-to-zero signal and for generating a clock signal from said differential serial data signals.
2. The receiver circuit as set forth in claim 1 , further comprising a T-type flip-flop, coupled to said clock recovery circuit, for receiving the clock signal of said clock recovery circuit and for generating a recovered clock signal by using the clock signal.
3. The receiver circuit as set forth in claim 2 , further comprising a data recovery circuit that includes an integrate and dump circuit for receiving said recovered clock signal and said differential serial data signals and for generating a recovered data bit stream.
4. The receiver circuit as set forth in claim 3 , wherein said recovered data bit stream is de-multiplexed.
5. The receiver circuit as set forth in claim 2 , wherein said recovered clock signal comprises a nominal duty cycle of 50% at half an input data rate of the differential serial data signals
6. The receiver circuit as set forth in claim 1 , further comprising a far-end termination circuit.
7. The receiver circuit as set forth in claim 1 , wherein said logic gate comprises an OR logic gate.
8. The receiver circuit as set forth in claim 1 , further comprising a low-power mode circuit for receiving a constant value on both differential serial data signals for a pre-determined period of time and for entering or exiting said low-power mode based on said constant value.
9. A circuit comprising:
a first integrated circuit chip comprising a transmitter for receiving data and for generating differential serial data signals that form a differential return-to-zero signal, wherein said differential return-to-zero signal comprises a first signal that transmits a high bit on a first differential link and a second signal that transmits a low bit on a second differential link, wherein said first and second signals comprise duty cycles less than 50%;
a second integrated circuit chip comprising:
an input circuit for receiving said differential serial data signal; and
a clock recovery circuit, coupled to said input circuit, comprising a logic gate for receiving said differential return-to-zero signal and for generating a clock signal from said differential return-to-zero signaling.
10. The circuit as set forth in claim 9 , wherein said second integrated circuit chip further comprises a T-type flip-flop, coupled to said clock recovery circuit, for receiving the clock signal of said clock recovery circuit and for generating a recovered clock signal by using the clock signal.
11. The circuit as set forth in claim 10 , wherein said second integrated circuit chip further comprises a data recovery circuit that includes an integrate and dump circuit for receiving said recovered clock signal and said differential serial data signals and for generating a differential recovered data bit stream.
12. The circuit as set forth in claim 10 , wherein said second integrated circuit chip further comprises a transmitter circuit for transmitting data to said first integrated circuit using said recovered clock signal to generate timing for said transmitter circuit.
13. The circuit as set forth in claim 9 , wherein said logic gate comprises an OR logic gate.
14. The circuit as set forth in claim 9 , wherein said second integrated circuit chip further comprises a far-end termination circuit.
15. The circuit as set forth in claim 9 , wherein:
said first integrated circuit chip comprising a master low-power mode circuit for transmitting a constant value on a plurality of the differential data signals for a pre-determined period of time to signal activation of a low-power mode on a slave device; and
said second integrated circuit chip comprising a slave low-power mode circuit for receiving said constant value on the plurality of the differential data signals for a pre-determined period of time and for entering or exiting said low-power mode based on said constant value.
16. A system comprising:
a master circuit comprising a plurality of transceiver circuits to transmit and receive, over a plurality of serial links, differential serial data signals that form a differential return-to-zero signal, wherein said differential return-to-zero signal comprises a first signal that transmits a high bit on a first differential link and a second signal that transmits a low bit on a second differential link, wherein said first and second signals comprise duty cycles less than 50%, said master circuit comprising a single phase-locked loop to generate timing signals for said transceiver circuits;
a plurality of slave circuits, each comprising:
an input circuit for receiving said differential serial data signals; and
a clock recovery circuit, coupled to said input circuit, comprising a logic gate for receiving said differential return-to-zero signal and for generating a clock signal from said differential return-to-zero signaling.
17. The system as set forth in claim 16 , wherein said slave circuits further comprise a T-type flip-flop, coupled to said clock recovery circuit, for receiving the clock signal of said clock recovery circuit and for generating a recovered clock signal by using the clock signal.
18. The system as set forth in claim 17 , wherein said slave circuits further comprise a data recovery circuit comprising an integrate and dump circuit for receiving said recovered clock signal and said differential serial data signals and for generating a recovered data bit stream.
19. The system as set forth in claim 17 , wherein said slave circuits further comprise a transmitter circuit for transmitting data to said first integrated circuit using said recovered clock signal to generate timing for said transmitter circuit.
20. The system as set forth in claim 16 , wherein said logic gate comprises an OR logic gate.
21. The system as set forth in claim 16 , wherein said slave circuits further comprise a far-end termination circuit.
22. A method of recovering a clock from a serial stream of data, said method comprising:
receiving differential serial data signals that form a differential return-to-zero signal, wherein said differential return-to-zero signal comprises a first signal that transmits a high bit on a first differential link and a second signal that transmits a low bit on a second differential link, wherein said first and second signals comprise duty cycles less than 50%; and
executing an OR logic operation between said differential serial data signals so as to recover a clock from said differential serial data signals.
23. A method of providing data and timing over a serial link and decoding said data, said method comprising:
receiving data;
generating a transmit clock signal;
encoding the data into a plurality of differential serial data signals that form a differential return-to-zero signal and are timed by the transmit clock signal, wherein said differential return-to-zero signal comprises a first signal that transmits a high bit on a first differential link and a second signal that transmits a low bit on a second differential link, wherein said first and second signals comprise duty cycles less than 50%;
providing the plurality of differential serial data signals over a serial link to a receiver;
receiving, at the receiver, said differential serial data signals;
executing an OR logic operation between said differential serial data signals so as to recover a clock from said differential serial data signals.