Semiconductor memory device
View Patent ↗A semiconductor memory device includes a plurality of banks # 0 to # 3 , a predecoder that generates a predecode signal, first latch circuits, each of which is assigned to the banks, that hold a first portion of the predecode signal, a main decoder that is assigned in common to the two banks, and receives a second portion of the predecode signal and outputs of the first latch circuits. The main decoder includes latch circuits that hold by each bank a decoded signal obtained by decoding the second portion of the predecode signal. In the present invention, an address through predecoder is used to latch a predecode signal, and hence it becomes possible to share one portion of the predecode signal between the banks.
1. A semiconductor memory device comprising:
a plurality of banks independently operable;
a predecoder that predecodes an address signal to generate a predecode signal including first and second portions;
first latch circuits, each of which is assigned to the plurality of banks, that hold the first portion of the predecode signal;
a main decoder that is assigned in common to at least two of the plurality of banks, and receives the second portion of the predecode signal and outputs of the first latch circuits, wherein
the main decoder includes second latch circuits that hold by each bank a decoded signal obtained by decoding the second portion of the predecode signal.
2. The semiconductor memory device as claimed in claim 1 , wherein the address signal is a row address, and the first portion of the predecode signal includes a main-word select predecode signal for selecting a main word line.
3. The semiconductor memory device as claimed in claim 2 , wherein the second portion of the predecode signal includes a memory-mat select predecode signal for selecting a memory mat and a sub-word select predecode signal for selecting a sub word line.
4. The semiconductor memory device as claimed in claim 3 , wherein the main decoder includes:
a main-word control circuit that generates a first internal signal by each bank based on at least the memory-mat select predecode signal and a bank select signal;
a main-word output circuit that generates a main-word-line select signal by each bank based on at least the main-word select predecode signal and the corresponding first internal signal; and
a sub-word control circuit that generates a sub-word-line select signal by each bank based on at least the sub-word select predecode signal and the bank select signal.
5. The semiconductor memory device as claimed in claim 4 , wherein the sub-word control circuit generates the sub-word-line select signal further based on the memory-mat select predecode signal.
6. The semiconductor memory device as claimed in claim 5 , wherein the second latch circuits includes:
a plurality of memory-mat select latch circuits, included in the main-word control circuit, that synchronize the memory-mat select predecode signal or a second internal signal obtained by decoding the memory-mat select predecode signal with the bank select signal and hold by each bank; and
a plurality of sub-word select latch circuits, included in the sub-word control circuit, that synchronize the sub-word select predecode signal or a third internal signal obtained by decoding the sub-word select predecode signal with the bank select signal and hold by each bank.
7. The semiconductor memory device as claimed in claim 4 , wherein the second latch circuits includes:
a plurality of memory-mat select latch circuits, included in the main-word control circuit, that synchronize the memory-mat select predecode signal or a second internal signal obtained by decoding the memory-mat select predecode signal with the bank select signal and hold by each bank; and
a plurality of sub-word select latch circuits, included in the sub-word control circuit, that synchronize the sub-word select predecode signal or a third internal signal obtained by decoding the sub-word select predecode signal with the bank select signal and hold by each bank.
8. The semiconductor memory device as claimed in claim 1 , wherein the main decoder is arranged between commonly assigned banks, and the predecode signal is formed along a longitudinal direction of the main decoder.
9. The semiconductor memory device as claimed in claim 8 , further comprising first and second pad electrode regions, both of which include a plurality of pad electrodes, wherein all the plurality of banks are positioned in an aligning manner between the first and second pad electrode regions.
10. The semiconductor memory device as claimed in claim 9 , wherein
the plurality of banks are divided into a first sub-bank region positioned on a side of the first pad electrode region and a second sub-bank region positioned on a side of the second pad electrode region,
data inputted and outputted via pad electrodes included in the first pad electrode region is read from or written into the first sub-bank region, and
data inputted and outputted via pad electrodes included in the second pad electrode region is read from or written into the second sub-bank region.
11. The semiconductor memory device as claimed in claim 10 , wherein reading from or writing into the first sub-bank region and reading from or writing into the second sub-bank region are performed simultaneously.
12. The semiconductor memory device as claimed in claim 1 , wherein in response to a refresh command, a refresh address is alternatively supplied to the banks to which the main decoder is commonly assigned.
13. The semiconductor memory device as claimed in claim 1 , wherein the predecoder is an address through type into which that the address is not latched at a stage before inputted.