System and apparatus for using test structures inside of a chip during the fabrication of the chip
The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.
1. A method for evaluating a fabrication of a semiconductor wafer, the method comprising:
identifying a location on a die of the wafer for each of a plurality of test structures;
when the wafer is in a partially fabricated form, generating a corresponding signal from each of the plurality of test structures by directing energy onto the individual test structures using a contactless medium;
measuring electrical or optical activity from at least some of the plurality of test structures on which the corresponding signal is generated;
correlating the measured electrical or optical activity for individual test structures to a corresponding performance parameter;
performing analysis using the performance parameter of each of the individual test structures in order to evaluate performance of one or more fabrication steps in the fabrication of the wafer.
2. The method of claim 1 , wherein generating a corresponding signal includes using illumination to generate the signal from each of the plurality test structures.
3. The method of claim 2 , wherein using illumination includes directing a laser onto a photodiode that is part of or connected to one or more of the plurality of test structures.
4. The method of claim 1 , wherein generating a corresponding signal includes using an e-beam to generate the signal from each of the plurality test structures.
5. The method of claim 1 , further comprising selecting a structure for one or more of the test structures to be indicative of a presence of an electrical or physical characteristic of the die and/or the wafer.
6. The method of claim 1 , wherein selecting a structure for one or more of the test structures includes selecting a dimension or arrangement of one or more ring oscillators that are to comprise an individual one of the test structures.
7. A method for evaluating a fabrication of a semiconductor wafer, the method comprising:
identifying a location on a die of the wafer for each of a plurality of test structures;
when the wafer is in a partially fabricated form, generating a corresponding signal from each of the plurality of test structures by directing energy onto the individual test structures using a contactless medium;
measuring electrical or optical activity from at least some of the plurality of test structures on which the corresponding signal is generated;
correlating the measured electrical or optical activity for individual test structures to a corresponding performance parameter;
performing analysis using the performance parameter of each of the individual test structures in order to evaluate a design of at least a portion of the wafer.
8. The method of claim 7 , further comprising performing analysis using the performance parameter of each of the individual test structures in order to evaluate a layout of at least a portion of the die.
9. The method of claim 7 , wherein generating a corresponding signal includes using illumination to generate the signal from each of the plurality test structures.
10. The method of claim 8 , wherein using illumination includes directing a laser onto a photodiode that is part of or connected to one or more of the plurality of test structures.
11. The method of claim 7 , wherein generating a corresponding signal includes using an e-beam to generate the signal from each of the plurality test structures.