IP Library Patent Application 11763001
Patent Application
App. No. 11/763,001

SYSTEM AND APPARATUS FOR USING TEST STRUCTURES INSIDE OF A CHIP DURING THE FABRICATION OF THE CHIP

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Quick Facts
Patent No.
US None
App. No.
11/763,001
Abstract

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Claims (17)

1 . An assembly for evaluating a fabrication of a semiconductor wafer, wherein the semiconductor wafer includes one or more test structures positioned on wafer at various locations including within at least one die of the wafer, and wherein the assembly comprises:

one or more energy sources located externally to the semiconductor wafer;

a control system that is configured to control the one or more energy sources into directing energy onto one or more energy receiving elements on one or more die of the wafer, wherein the energy is suitable to activate the one or more test structures;

a detector system comprising one or more detectors, the detector system being configured to measure electrical activity from the one or more test structures that are activated by the direction of energy from the one or more energy sources in order to determine a performance parameter value for each of the one or more test structures;

a data processing unit that interprets electrical activity detected by the detector system and identifies a correlation between the performance parameter value and one or more fabrication steps or sequences of the fabrication.

2 . The assembly of claim 1 , wherein the assembly is configured to operate when the test structures are disposed on the wafer in a partially-fabricated state.

3 . The assembly of claim 2 , wherein the data processing unit determines a variance of the performance parameter value for multiple test structures located in the plurality of locations.

4 . The assembly of claim 3 , wherein the variance identifies one or more process variations in the fabrication.

5 . The assembly of claim 1 , wherein the detector system includes a photon detector that is configured to detect photons from the one or more test structures when the one or more test structures are activated.

6 . The assembly of claim 5 , wherein the photon detector is configured to detect photons emitted from a gate of a transistor that forms at least a part of the one or more test structures.

7 . The assembly of claim 1 , wherein the detector system includes a radio-frequency detector that detects a radio-frequency transmission that is converted from an output of the one or more test structures.

8 . The assembly of claim 1 , wherein the detector system includes an electron-beam that detects secondary electron emissions that are modulated by the output of the one or more test structures.

9 . The assembly of claim 1 , wherein the control system receives a feedback from the chip on the sufficiency of the energy from the one or more energy sources.

10 . The assembly of claim 1 , wherein the control system adjusts the energy directed from the one or more energy sources in response to receiving the feedback.

11 . The assembly of claim 1 , wherein the one or more energy sources includes a first laser that is configured to produce a modulating beam and a second laser that is configured to produce a constant beam.

12 . The assembly of claim 1 , wherein the performance parameter value is based on a signal delay.

13 . The assembly of claim 1 , wherein the control system is configured to control the one or more energy sources into causing the generation of a test signal and a power signal from within the die.

Assignments (2)
SECURITY AGREEMENT Recorded Sep 20, 2011
From: TAU-METRIX, INC.
To: TEL VENTURE CAPITAL, INC.
Reel/Frame 026934/0237 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2007
From: AGHABABAZADEH, MAJID; ESTABIL, JOSE J; PAKDAMAN, NADER; STEINBRUECK, GARY L; VICKERS, JAMES S
To: TAU-METRIX, INC.
Reel/Frame 019429/0850 →