IP Library Granted Patent US 7,772,099
Granted Patent B2
US 7,772,099 · App. 11/765,145 · Granted Aug 10, 2010

Method for manufacturing a semiconductor device having a doped silicon film

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Quick Facts
Patent No.
US 7,772,099
App. No.
11/765,145
Granted
Aug 10, 2010
Kind
B2
Abstract

A method for manufacturing a semiconductor device includes the step of depositing a doped silicon layer doped with a first-conductivity-type dopant and a non-doped silicon layer to form a layered silicon film, implanting a first-conductivity-type dopant into a portion of the layered silicon film disposed in a first region, implanting a second-conductivity-type dopant into a portion of the layered silicon film disposed in a second region, and heat treating the layered silicon film to form a first-conductivity-type silicon film in the first region and a second-conductivity-type silicon film in the second region.

Claims (9)

1. A method for manufacturing a semiconductor device comprising:

consecutively depositing a doped silicon layer doped with a first-conductivity-type dopant and a non-doped silicon layer to form a layered silicon film overlying a silicon substrate, said silicon substrate including a first region and a second region;

implanting a first-conductivity-type dopant into a portion of said layered silicon film in said first region;

implanting a second-conductivity-type dopant into a portion of said layered silicon film in said second region; and

heat treating said layered silicon film to form a first-conductivity-type silicon film in said first region and a second-conductivity-type silicon film in said second region.

2. The method according to claim 1 , further comprising, before said depositing, forming a recess in said first region of said silicon substrate, wherein said depositing deposits said doped silicon layer and said non-doped silicon layer on said silicon substrate including an internal of said recess, and said non-dope silicon film has a substantially flat top surface.

3. The method according to claim 2 , wherein said doped silicon layer has a thickness larger than half a minimum width of said recess.

4. The method according to claim 1 , further comprising depositing a metallic film on said layered silicon film before or after said heat treatment.

5. The method according to claim 4 , further comprising patterning said layered silicon film and said metallic film to form a gate electrode of a MOSFET.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2007
From: SAINO, KANTA
To: ELPIDA MEMORY, INC.
Reel/Frame 019450/0758 →