Semiconductor die having a distribution layer
View Patent ↗A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.
1. A semiconductor die, comprising:
an integrated circuit; and
a redistribution pattern formed over the integrated circuit, the redistribution pattern redistributing a die bond pad from a first location on a surface of the semiconductor die to a second location on the surface of the semiconductor die, the redistribution pattern including:
an adhesive material adhered to a surface of the semiconductor die in a pattern of the redistribution pattern, and
conductive material deposited on the adhesive material.
2. A semiconductor die as recited in claim 1 , wherein the conductive material is at least one of titanium and aluminum.
3. A semiconductor die as recited in claim 1 , wherein the conductive material has a thickness of between 1 and 5 microns on the adhesive material.
4. A semiconductor die as recited in claim 1 , wherein the conductive material has a thickness of between 1 and 3 microns on the adhesive material.
5. A semiconductor die as recited in claim 1 , wherein the adhesive material is adhered to the surface of the semiconductor die in the pattern of the redistribution pattern by a laser heating the adhesive material in the pattern of the redistribution pattern.
6. A semiconductor die as recited in claim 1 , wherein the integrated circuit is a flash memory circuit.
7. A semiconductor die as recited in claim 1 , wherein the integrated circuit is a controller circuit for a flash memory.
8. A semiconductor die, comprising:
an integrated circuit;
a bond pad at a first location coupled to the integrated circuit; and
a redistribution pattern formed over the integrated circuit for electrically coupling the bond pad from the first location to a second location on the semiconductor die, the redistribution pattern including:
a pattern of adhesive material formed from a layer of adhesive material applied to a surface of the semiconductor die, portions of the layer of adhesive material being removed to leave the pattern of the adhesive material by heating the adhesive material in the pattern of the redistribution pattern and removing portions of the adhesive layer not heated by the laser, and
conductive material deposited on the pattern of adhesive material.
9. A semiconductor die as recited in claim 8 , wherein the conductive material is at least one of titanium and aluminum.
10. A semiconductor die as recited in claim 8 , wherein the conductive material has a thickness of between 1 and 5 microns on the adhesive material.