Semiconductor device and method of manufacturing the same
View Patent ↗A conventional semiconductor device has a problem that it is difficult to obtain a desired breakdown voltage characteristic due to a reduction in a punch-through breakdown voltage between drain and source regions. In a semiconductor device according to the present invention, a P type diffusion layer is formed in an N type epitaxial layer. An N type diffusion layer as a back gate region is formed in the P type diffusion layer. The N type diffusion layer is formed by self-alignment using a drain electrode. This structure makes it possible to increase an impurity concentration of the N type diffusion layer in a vicinity of a P type diffusion layer as a source region. As a result, it is possible to improve a punch-through breakdown voltage between the drain and the source regions, and to achieve a desired breakdown voltage characteristic of the MOS transistor.
1. A semiconductor device comprising:
a semiconductor layer;
a drain region, which is formed in the semiconductor layer;
a source region, which is formed in the semiconductor layer;
a back gate region, which is formed in the semiconductor layer;
a gate oxide film formed on the semiconductor layer; and
a gate electrode formed on the gate oxide film, wherein
a first diffusion layer of one conductivity type is formed in the semiconductor layer so as to extend across regions where the drain region and the back gate region are formed,
a diffusion layer of an opposite conductivity type constituting the back gate region is formed in the first diffusion layer of the one conductivity type,
a second diffusion layer of the one conductivity type constituting the source region is formed in the diffusion layer of the opposite conductivity type, and
an impurity concentration peak of the diffusion layer of the opposite conductivity type is formed in a deeper portion of the first diffusion layer of the one conductivity type than a junction region between the diffusion layer of the opposite conductivity type and the second diffusion layer of the one conductivity type.
2. The semiconductor device according to claim 1 wherein,
an impurity concentration in a vicinity of a bottom surface of the second diffusion layer of the one conductivity type is 0.8 times or more as high as that in a vicinity of a top surface of the second diffusion layer of the one conductivity type among impurity concentrations of the diffusion layer of the opposite conductivity type in a vicinity of the junction region.
3. The semiconductor device according to claim 1 wherein
the gate electrode is formed of a polysilicon film and a tungsten silicon film, and
the tungsten silicon film has a thickness greater than that of the polysilicon film.
4. A method of manufacturing a semiconductor device, comprising the steps of:
forming a first diffusion layer of one conductivity type in a semiconductor layer, and forming a gate oxide film and a gate electrode on the semiconductor layer, and then forming a diffusion layer of an opposite conductivity type constituting a back gate region in the first diffusion layer of the one conductivity type by self-alignment using the gate electrode; and
forming a second diffusion layer of the one conductivity type constituting a source region in the diffusion layer of the opposite conductivity type in a manner that the second diffusion layer of the one conductivity type overlapping the diffusion layer of the opposite conductivity type, and forming a third diffusion layer of the one conductivity type constituting a drain region in the first diffusion layer of the one conductivity type; wherein,
in the step of forming the diffusion layer of the opposite conductivity type, an impurity concentration peak of the diffusion layer of the opposite conductivity type is formed in a portion of the first diffusion layer of the one conductivity type deeper than a junction region between the diffusion layer of the opposite conductivity type and the second diffusion layer of the one conductivity type.
5. The method of manufacturing a semiconductor device according to claim 4 , wherein the step of forming the diffusion layer of the opposite conductivity type includes the step of performing ion implantation at an accelerating voltage of 80 to 160 (KeV).
6. The method of manufacturing a semiconductor device according to claim 4 , wherein, in the step of forming the gate electrode, a tungsten silicon film is deposited on a polysilicon film in a manner that the tungsten silicon film has a thickness greater than that of the polysilicon film.