IP Library Granted Patent US 7,648,904
Granted Patent B2
US 7,648,904 · App. 11/770,681 · Granted Jan 19, 2010

Metal line in semiconductor device and method for forming the same

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Quick Facts
Patent No.
US 7,648,904
App. No.
11/770,681
Granted
Jan 19, 2010
Kind
B2
Abstract

A metal line in a semiconductor device includes an insulation layer having trenches formed therein, a barrier metal layer formed over the insulation layer and the trenches, a metal layer formed over the barrier metal layer, wherein the metal layer fills the trenches, and an anti-galvanic corrosion layer formed on an interface between the metal layer and the barrier metal layer.

Claims (33)

1. A method for forming a metal line in a semiconductor device, the method comprising:

providing a substrate including an insulation layer having a plurality of trenches formed therein;

forming a barrier metal layer over the insulation layer and the trenches;

forming a first metal layer over the barrier metal layer;

forming a second metal layer over the first metal layer, wherein the second metal layer fills the trenches; and

forming an anti-galvanic corrosion layer on an interface between the barrier metal layer and the second metal layer using a thermal process.

2. The method of claim 1 , wherein the anti-galvanic corrosion layer comprises an alloy layer including combined materials of the first and second metal layers.

3. The method of claim 1 , wherein the first metal layer comprises a first metal and the second metal layer comprises a second metal, the first metal and the second metal having opposite polarities.

4. The method of claim 1 , wherein the first metal layer comprises copper (Cu) and the second metal layer comprises aluminum (Al).

5. The method of claim 1 , wherein the barrier metal layer comprises a stack structure comprising a material selected from a group consisting of titanium (Ti)/titanium nitride (TiN), Ti/TiN/Ti, tantalum (Ta)/tantalum nitride (TaN), Ta/TaN/Ta, Ti/titanium silicon nitride (TiSiN), and Ti/TiSiN/Ti.

6. The method of claim 1 , further comprising, after forming the anti-galvanic corrosion layer:

performing a chemical mechanical polishing (CMP) process on the second metal layer to isolate adjacent portions of the second metal layer; and

performing a cleaning process.

7. The method of claim 6 , wherein performing the CMP process comprises oxidizing the second metal layer and removing portions of the oxidized second metal layer formed over the insulation layer using a polish slurry having a pH ranging from approximately 4 to approximately 6.

8. The method of claim 7 , wherein the CMP process comprises adding an oxidizer of approximately 2 wt % to approximately 6 wt % to oxidize the second metal layer, the polish slurry comprising colloidal silica or aluminum oxide-based polish particles.

9. The method of claim 6 , wherein performing the cleaning process comprises adding one selected from a group consisting of a metal corrosion inhibitor, an amine-based hydrazine, and hydrogen fluoride (HF), to a deionized water cleaning solution such that the cleaning solution is a basic solution.

10. The method of claim 9 , wherein the metal corrosion inhibitor comprises methyl gallate.

11. A method for forming a metal line in a semiconductor device, the method comprising:

providing a substrate including an insulation layer having a plurality of trenches formed therein;

forming a barrier metal layer over the insulation layer and the trenches; and

forming a metal layer including a first metal over the barrier metal layer, the metal layer filling the trenches,

wherein a gas including a second metal is supplied when forming the metal layer to form an anti-galvanic corrosion layer on an interface between the barrier metal layer and the metal layer.

12. The method of claim 11 , wherein the anti-galvanic corrosion layer comprises an alloy layer including a combination of the first and second metals.

13. The method of claim 11 , wherein the first metal and the second metal have opposite polarities.

14. The method of claim 11 , wherein the first metal comprises aluminum (Al) and the second metal comprises copper (Cu).

15. The method of claim 11 , wherein the barrier metal layer comprises a stack structure comprising a material selected from a group consisting of titanium (Ti)/titanium nitride (TiN), Ti/TiN/Ti, tantalum (Ta)/tantalum nitride (TaN), Ta/TaN/Ta, Ti/titanium silicon nitride (TiSiN), and Ti/TiSiN/Ti.

16. The method of claim 11 , further comprising, after forming the metal layer:

performing a chemical mechanical polishing (CMP) process on the metal layer to isolate adjacent portions of the metal layer; and

performing a cleaning process.

17. The method of claim 16 , wherein performing the CMP process comprises oxidizing the metal layer and removing portions of the oxidized metal layer formed over the insulation layer using a polish slurry having a pH ranging from approximately 4 to approximately 6.

18. The method of claim 17 , wherein the CMP process comprises adding an oxidizer of approximately 2 wt % to approximately 6 wt % to oxidize the metal layer, the polish slurry comprising colloidal silica or aluminum oxide-based polish particles.

19. The method of claim 16 , wherein performing the cleaning process comprises adding one selected from a group consisting of a metal corrosion inhibitor, an amine-based hydrazine, and hydrogen fluoride (HF), to a deionized water cleaning solution such that the cleaning solution is a basic solution.

20. The method of claim 19 , wherein the metal corrosion inhibitor comprises methyl gallate.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE IS HYNIX SEMICONDUCTOR INC. NOT HYNIX-SEMICONDUCTOR INC. THERE IS NO HYPHEN IN THE NAME. PREVIOUSLY RECORDED ON REEL 67328 FRAME 814. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded May 14, 2024
From: HYNIX SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067412/0482 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067369/0832 →
CHANGE OF NAME Recorded May 6, 2024
From: HYNIX-SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067328/0814 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2007
From: CHOI, YOUNG-SOO; KIM, GYU-HYUN
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 019570/0238 →