Multi-level operation in dual element cells using a supplemental programming level
The claimed subject matter provides systems and/or methods that facilitate programming and reading multi-level, multi-bit memory cells in a memory device. In multi-bit memory cells, programming one element can affect the second element. Certain combinations of elements can cause excessive levels of complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb, reducing memory device reliability. Such effects may be pronounced where a high charge level is programmed into a first element while a second element of the same memory cell is unprogrammed. Memory cell elements can be programmed using additional charge levels to mitigate such effects. For example, the sixteen distinct element combinations possible using four charge levels can be mapped to a subset of twenty-five possible element combinations using five charge levels, avoiding element combinations likely to generate excessive complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb.
1. A system that facilitates programming memory utilizing multi-level, multi-bit memory cells, comprising:
a translation component that maps an element pair encoded using a first set of levels to a second set of levels so as to reduce the occurrence of potentially discordant element pairs, the number of levels in the second set is greater than the first set, the translation component replaces an unprogrammed element with a high threshold voltage level of the second set; and
a program component that programs at least one element of a multi-bit memory cell based upon the mapped element pair.
2. The system of claim 1 , the first set of levels utilizes four distinct threshold voltage levels and the second set of levels utilizes at least five distinct threshold voltage levels.
3. The system of claim 1 , further comprising an identification component that identifies the element pair as potentially discordant.
4. The system of claim 3 , further comprising a mapping component that maps the potentially discordant element pair to a distinct element pair combination.
5. The system of claim 1 , the potentially discordant element pair comprises an unprogrammed element and a high threshold voltage level element.
6. The system of claim 1 , further comprising a translation table that maps the first set of levels to the second set of levels.
7. A system that facilitates memory utilizing multi-bit memory cells, comprising:
a read component that reads at least one element value of a multi-bit memory cell, at least one element value is a function of a first set of levels; and
a translation component that adjusts the element value as a function of a second set of levels, the second set of levels contains fewer levels than the first set of levels and a mapping from the second set to the first set eliminates a potentially discordant element pair combination wherein an unprogramed state is replaced with the highest level charge.
8. The system of claim 7 , the first set utilizes five levels of charge and the second set utilizes four levels of charge.
9. The system of claim 7 , the potentially discordant element pair combination includes a high level charge element and a blank level element.
10. The system of claim 7 further comprises a translation table that maps the second set to the first set.
11. A method for programming a multi-level, multi-bit memory cell, comprising:
obtaining an element pair encoded based upon a set of data levels;
translating the element pair to a set of program levels, number of levels in the program set is greater than number of levels in the data set so as to decrease occurrences of potentially discordant combinations;
replacing an unprogrammed state with the highest level charge; and
programming the memory cell with the translated element pair.
12. The method of claim 11 , the data set includes four levels of charge and the program level of combinations includes five levels of charge.
13. The method of claim 11 , farther comprising identifying the element pair as a potentially discordant combination.
14. The method of claim 13 , further comprising mapping the potentially discordant combination to the program set utilizing a translation table.
15. The method of claim 14 , the potentially discordant combination comprises a combination of an unprogrammed state and a higher level charge.
16. The method of claim 15 , the potentially discordant combination includes at least one of a level three element and a level four element.
17. A system for reading a multi-level, multi-bit memory cell, comprising:
means for reading an element value encoded using a first set of levels;
means for adapting the element value to a second set of levels, the number of levels in the first set is greater than number of levels in the second set and a mapping of the second set to the first set eliminates at least one potentially discordant element pair combination; and
means for an unprogrammed state with the highest level charge.
18. The system of claim 9 , the first set of levels uses five charge levels and the second set of levels utilizes four charge levels.
19. The system of claim 1 , an element pair that is not potentially discordant remains unchanged.
20. The system of claim 1 , further comprising a voltage generator component that is operable to generate necessary voltages for programming the multi-bit memory cells.