Asymmetric cryptographic device with local private key generation and method therefor
An asymmetric cryptographic integrated circuit 20 and a data processing device 10 in which the integrated circuit 20 is used are disclosed. A security boundary 44 is confined to the interior of integrated circuit 20 . A random number generator 50 with a hardware entropy source 54 and an arithmetic unit 62 programmed through microcode 38″ to perform a variety of cryptographically useful functions are included within security boundary 44 . One of these functions is a primality tester 72 . A controller 36 for integrated circuit 20 may cause cryptographically sensitive data, such as large random prime numbers and a clear private key to be generated within the confines of security boundary 44 . A symmetric key encryption engine 56 is included within security boundary 44 and used to encrypt the clear private key so that a resulting encrypted private key may be stored outside security boundary 44 in a non-volatile memory 12.
1. A data processing device which provides asymmetric cryptographic functions, said device comprising:
an untrustworthy storage section configured for read and write operations;
an untrustworthy input/output section coupled to said processor section and configured to obtain data from outside said device and to provide data outside said device; and
an asymmetric-key, cryptographic integrated circuit coupled to said storage section and said input/output section, said integrated circuit imposing a security boundary that is entirely contained within said integrated circuit and untrustworthy circuits including a processor section located within said integrated circuit and outside said security boundary, said processor section being configured to execute computer software instructions obtained from outside said security boundary, and said integrated circuit being configured in response to microcode confined inside said security boundary to generate random prime numbers and a clear private key within said security boundary, and said integrated circuit being configured in response to said microcode to prevent said random prime numbers and said clear private key from being detected from outside said security boundary, wherein said integrated circuit comprises:
a integrated circuit package;
a semiconductor substrate embedded within said package;
a random number generator formed on said substrate inside said security boundary and embedded within said package;
a primality tester formed on said substrate inside said security boundary and embedded within said package;
a non-volatile source of a symmetric key, said symmetric-key source being located within said security boundary;
an encryption engine located within said security boundary, coupled to said symmetric-key source and configured to encrypt said clear private key using said symmetric key to produce an encrypted private key; and
a controller formed on said substrate and embedded within said package, said controller being coupled to said random number generator, to said primality tester, and to said processor section, and said controller serving as a gateway through said security boundary;
wherein said controller is configured in response to said microcode to send data outside said security boundary to said processor section, to receive data from said processor section, to manage said random number generator and said primality tester to generate said clear private key, to block said clear private key from being detected from outside said security boundary, and to send said encrypted private key outside said security boundary for storage.