IP Library Granted Patent US 7,754,563
Granted Patent B2
US 7,754,563 · App. 11/776,300 · Granted Jul 13, 2010

Nanolaminate-structure dielectric film forming method

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Quick Facts
Patent No.
US 7,754,563
App. No.
11/776,300
Granted
Jul 13, 2010
Kind
B2
Abstract

Nanolaminate-structure SrO/TiO films are formed on a lower electrode of a capacitor by molecular layer deposition kept in a rate-determined state by a surface reaction. The nanolaminate-structure SrO/TiO films are formed by alternately laminating one or more and 20 or less SrO molecular layers and one or more and 20 or less TiO molecular layers at 150° C. or more and 400° C. or less and at 10 Torr or more and the atmospheric pressure or less. This makes it possible to obtain the nanolaminate-structure SrO/TiO films with a high permittivity and a high coverage and with no occurrence of crystalline foreign substance.

Claims (25)

1. A method of forming a dielectric film on a semiconductor substrate held in a reaction chamber, the method comprising:

repeating, a plurality of times, a sequence of steps comprising a first deposition step, a first purging step, a second deposition step and a second purging step in that order, to form a dielectric film having a predetermined thickness:

the first deposition step performing molecular layer deposition to form a first metal oxide film by simultaneously supplying a first metal material gas and an oxidizing gas to the reaction chamber;

the first purging step of purging the first metal material gas and the oxidizing gas out of the reaction chamber;

the second deposition step performing molecular layer deposition to form a second metal oxide film by simultaneously supplying a second metal material gas and an oxidizing gas to the reaction chamber; and

the second purging step of purging the second metal material gas and the oxidizing gas out of the reaction chamber.

2. The method according to claim 1 , wherein said first and second molecular layer deposition steps each perform the molecular layer deposition kept in a rate-determined state by surface reaction.

3. The method according to claim 1 , wherein said first and second deposition steps each deposit one or more and 10 or less molecules in a film thickness direction to form a molecular layer.

4. The method according to claim 1 , wherein said first and second deposition steps are alternately repeated to form one or more and 20 or less molecular layers of said first metal oxide and one or more and 20 or less molecular layers of said second metal oxide.

5. The method according to claim 1 , wherein said first metal oxide is strontium oxide and said second metal oxide is titanium oxide.

6. The method according to claim 5 , wherein the strontium oxide film is formed under conditions such that a temperature of said semiconductor substrate is from about 150° C. to about 425° C. and a pressure in said reaction chamber is from about 1.33×10 3 Pa to about and 1.01×10 5 Pa.

7. The method according to claim 5 , wherein the titanium oxide film is formed under conditions such that a temperature of said semiconductor substrate is from about 150° C. to about 475° C. and a pressure in said reaction chamber is from about 1.33×10 3 Pa to about 1.01×10 5 Pa.

8. The method according to claim 5 , wherein the strontium oxide film and the titanium oxide film are each formed under conditions such that a temperature of said semiconductor substrate is from about 150° C. to about 400° C. and a pressure in said reaction chamber is from about 1.33×10 3 Pa to about 1.01×10 5 Pa.

9. The method according to claim 5 , wherein the strontium oxide film and the titanium oxide film are each formed under conditions such that a temperature of said semiconductor substrate is from about 350° C. to about 400° C. and a pressure in said reaction chamber is from about 1.33×10 3 Pa to about 1.33×10 4 Pa.

10. The method according to claim 1 , further comprising forming a first dielectric film on said dielectric film as its lower or upper layer.

11. The method according to claim 10 , wherein said first dielectric film is made of aluminum oxide.

12. A semiconductor device comprising a capacitor which includes the dielectric film formed by the method according to claim 1 .

13. A method of manufacturing a capacitor of a semiconductor device by using the method according to claim 5 , wherein said strontium oxide is formed by using one of Sr (METHD) 2 , Sr (THD) 2 , Sr (C 5 —Pr 3 H 2 ), and Sr (DPM) 2.2tetraene is used as a Sr material gas.

14. A method of manufacturing a capacitor of a semiconductor device by using the method according to claim 5 , wherein said titanium oxide is formed by one of Ti (MPD) (THD) 2 , Ti (O-i-Pr) 4 , and Ti (O-i-Pr)2(THD) as a Ti material gas.

15. A method of manufacturing a capacitor of a semiconductor device by using the method according to claim 1 , wherein one of O 2 plasma, O 3 , H 2 , and H 2 O plasma is used as an oxidizing gas.

16. A method of manufacturing a capacitor of a semiconductor device by using the method according to claim 11 , wherein said aluminum oxide is formed by atomic layer deposition (ALD).

17. A method of manufacturing a capacitor of a semiconductor device by using the method according to claim 11 , wherein said aluminum oxide is formed by using trimethylaluminum (TMA) as an Al material gas.

18. A method of manufacturing a capacitor of a semiconductor device by using the method according to claim 11 , wherein said aluminum oxide is formed by using one of O 3 , H 2 O, and O2 plasma as an oxidizing gas.

19. A method of manufacturing a capacitor of a semiconductor device by using the method according to claim 1 , wherein O 2 is used as an oxidizing gas.

20. A method of manufacturing a capacitor of a semiconductor device according to claim 12 , wherein, after the formation of at least one of the dielectric film and an upper electrode, a heat treatment is performed at 500° C. to 600° C. in an inert atmosphere.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2007
From: NAKANISHI, NARUHIKO
To: ELPIDA MEMORY, INC.
Reel/Frame 019544/0013 →