Method of fabricating semiconductor integrated circuit device with 99.99 wt% cobalt
A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
1. A method of fabricating a semiconductor integrated circuit device, comprising the steps of:
(a) forming an isolation groove in a silicon surface of a first major surface of a wafer, so as to divide the silicon surface into two regions which are to be first and second regions;
(b) after step (a), forming a first insulating film of silicon oxide by chemical vapor deposition in such manner that the first insulating film covers the silicon surface;
(c) after step (b), polishing the first insulating film so as to planarize the first major surface of the wafer;
(d) after step (c), forming two gate electrodes having a gate length less than 250 nm, to be N- and P-type gate electrodes, respectively over the first and second regions, each of said two gate electrodes having a silicon film to be a silicon conductive film;
(e) forming N-type source and drain regions in the first region, said N-type source and drain regions to constitute a first insulated gate field effect transistor together with the N-type gate electrode and a pair of first insulating side walls;
(f) forming P-type source and drain regions in the second region, said P-type source and drain regions to constitute a second insulated gate field effect transistor together with the P-type gate electrode and a pair of second insulating side walls;
(g) after the steps (d), (e), and (f), exposing surface portions of the silicon surface over said N-type and P-type source regions and drain regions;
(h) after the step (g), depositing a cobalt film covering at least the exposed surface portions, by sputtering, from a cobalt sputtering target which, apart from carbon and oxygen impurities, is at least 99.99 wt. % pure, wherein a sum of Fe and Ni in the cobalt film sputtering target is not greater than 50 ppm by weight, and wherein the sputtering is performed in such a manner that the composition of the deposited cobalt film is substantially the same as that of the cobalt sputtering target;
(i) after the step (h), performing first rapid thermal annealing at a first temperature to the first major surface formed with the cobalt film so as to form cobalt monosilicide films over the surface portions, leaving a remaining cobalt film not formed into cobalt monosilicide, wherein the first temperature is a temperature that creep-up across the first and second insulating side walls substantially does not take place;
(j) after the step (i), removing the remaining cobalt film by wet etching;
(k) after the step (j), performing second rapid thermal annealing at a second temperature higher than the first temperature to the first major surface so as to form cobalt disilicide films over the surface portions;
(l) after the step (k), forming a second insulating film over the silicon surface;
(m) after the step (l), forming a third insulating film over the second insulating film such that the third insulating film has a thickness greater than a thickness of the second insulating film; and
(n) after the step (l), performing a thermal annealing to the wafer.
2. A method of fabricating a semiconductor integrated circuit device according to claim 1 , the step (m) comprising the substeps of:
(o) after the step (l), forming a fourth insulating film over the second insulating film;
(p) after the step (o), polishing the fourth insulating film so as to planarize the fourth insulating film; and
(q) after the step (p), forming a fifth insulating film over the fourth insulating film such that the third insulating film has a thickness greater than a thickness of the second insulating film.
3. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein the first temperature is not higher than 525 degrees centigrade.
4. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein the cobalt sputtering target includes a sum of Fe and Ni which is not greater than 10 ppm by weight.
5. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein said cobalt sputtering target, apart from carbon and oxygen impurities, is 99.999 wt. % pure.
6. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein the first temperature is not lower than 475 degrees centigrade.
7. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein the semiconductor integrated circuit device is designed under design rules not larger than 0.25 micron.
8. A method of fabricating a semiconductor integrated circuit device according to claim 7 , wherein the cobalt sputtering target, apart from carbon and oxygen impurities, is 99.999 wt. % pure.
9. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein the second temperature is from 650 degrees centigrade to 800 degrees centigrade.
10. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein said P-type gate electrode is doped with boron.