Semiconductor memory device and manufacturing method thereof
View Patent ↗A semiconductor memory device is provided in which a phase-change layer can be formed stably and electric current required to cause the phase change of the phase-change layer can be reduced. An edge portion of the phase-change layer is formed above a lower electrode. The edge portion is formed to assume a tapered shape in cross section such that the thickness of the phase-change layer varies above the contact area between the lower electrode and the phase-change layer. The tapered portion is filled with an oxide film. According to this configuration, the region in which the phase-change occurs can be restricted, and hence the phase-change layer can be heated efficiently, resulting in reduction of electric current required for heating.
1. A semiconductor memory device comprising:
a phase-change layer provided between a lower electrode and an upper electrode,
wherein the phase-change layer has a tapered portion located above the lower electrode, and an area of an uppermost flat surface of the phase-change layer is less than an area of a lower most flat surface of the phase-change layer, and
wherein the lower electrode comprises a ring shape in a plan view, the tapered portion of the phase-change layer being inclined in a direction away from an inside of the ring shape and toward an outside of the ring shape and including a part which is formed over the ring shape in the plan view.
2. The semiconductor memory device according to claim 1 , wherein the tapered portion is located above a region where the lower electrode is in contact with the phase-change layer.
3. The semiconductor memory device according to claim 1 , wherein the tapered portion is filled with an oxide film.
4. The semiconductor memory device according to claim 3 , wherein the lower electrode comprises a cup-shaped electrode and includes a tapered portion having a shape which is defined by cutting off a part of the cup-shaped electrode, the shape of the tapered portion of the lower electrode being the same as a shape of the tapered portion of the phase-change layer.
5. The semiconductor memory device according to claim 1 , wherein the lower electrode comprises a cup-shaped electrode and includes a tapered portion having a shape which is defined by cutting off a part of the a cup-shaped electrode, the shape of the tapered portion of the lower electrode being the same as a shape of the tapered portion of the phase-change layer.
6. The semiconductor memory device according to claim 5 , wherein the phase-change layer comprises a chalcogenide.
7. The semiconductor memory device according to claim 1 , wherein the phase-change layer comprises a chalcogenide.
8. The semiconductor memory device according to claim 3 , wherein the phase-change layer comprises a chalcogenide.
9. The semiconductor memory device according to claim 4 , wherein the phase-change layer comprises a chalcogenide.
10. A semiconductor memory device, comprising:
a lower electrode which has a cup shape;
a phase-change layer disposed on the lower electrode and connected to a part of a top surface of the lower electrode; and
an upper electrode disposed on a top surface of the phase-change layer,
wherein the phase-change layer has a side surface between the lower electrode and the upper electrode, and a part of the side surface being located above the lower electrode has a tapered shape, and
wherein the lower electrode comprises a ring shape in a plan view, the tapered shape of the side surface of the phase-change layer being inclined in a direction away from an inside of the ring shape and toward an outside of the ring shape and including a part which is formed over the ring shape in the plan view.
11. The semiconductor memory device according to claim 10 , further comprising:
a first insulation layer, the lower electrode being disposed in the first insulation layer, and the top surface of the lower electrode being exposed at a top surface of the first insulation layer; and
a second insulation layer disposed on the first insulation layer,
wherein the tapered shape side surface of the phase-change layer is covered by the second insulation layer.
12. The semiconductor memory device according to claim 11 , wherein the second insulation layer has a plane top surface, a level of a top surface of the upper electrode and a level of the top surface of the second insulation layer being substantially same.
13. The semiconductor memory device according to claim 10 , wherein the top surface of the lower electrode has the ring shape in plan view, the phase-change layer being extended to an outward direction from an outer edge of the ring shape in plan view.
14. The semiconductor memory device according to claim 1 , wherein the tapered portion of the phase-change layer includes another part which is formed inside the ring shape in the plan view.
15. The semiconductor memory device according to claim 1 , wherein the upper electrode comprises an edge portion which is formed outside the ring shape in the plan view and contacts the tapered portion of the phase-change layer.
16. The semiconductor memory device according to claim 1 , wherein the upper electrode comprises a tapered portion, a shape of the tapered portion of the upper electrode being the same as a shape of the tapered portion of the phase-change layer.
17. The semiconductor memory device according to claim 16 , wherein the lower electrode comprises a cup-shaped lower electrode, and
wherein the memory device further comprises an insulation film formed in the cup-shaped lower electrode, the tapered portion of the phase-change layer being formed on a surface of the insulation film and extending from the surface of the insulation film to the tapered portion of the upper electrode.
18. The semiconductor memory device according to claim 17 , wherein the cup-shaped lower electrode comprises a bottom portion and a wall portion formed perpendicular to the bottom portion, the tapered portion of the phase-change layer being formed over the wall portion of the cup-shaped lower electrode.
19. The semiconductor memory device according to claim 16 , wherein the tapered portion of the phase-change layer is aligned with the tapered portion of the upper electrode.
20. The semiconductor memory device according to claim 1 , wherein a region of the phase-change layer where phase change occurs is formed between the tapered portion of the phase-change layer and the lower electrode.