Granted Patent B2

US 8,239,429 · App. 11/786,424 · Granted Aug 7, 2012

Abstract

Claims (81)

1. Output buffer into which first and second input signals are applied and that delivers an output signal, said output signal being switchable between a high logical level and a low logical level, and vice versa, said buffer comprising a first switching stage comprising:

first high switching means to switch said output signal from said low logical level to said high logical level;

first low switching means to switch said output signal from said high logical level to said low logical level;

first high and low control means acting on said first high and low switching means respectively, said first high and low control means receiving said first and second input signals, respectively;

first high and low memory points,

the output from the first high control means and the input to said first high switching means being connected to the first high memory point, the first high memory point further connected to the first low control means and to a second high control means,

the output from the first low control means and the input to said first low switching means being connected to the first low memory point, the first low memory point further connected to the first high control means and to a second low control means;

wherein said buffer comprises a second offset switching stage installed in cascade downstream from said first switching stage and comprising:

second high switching means of said output signal;

second low switching means of said output signal; and

second high and low control means acting on said second high and low switching means respectively, through upstream high and low control points respectively, said second high and low control means receiving said first and second input signals respectively, said upstream high and low control points being delayed in time with respect to said high and low memory points, respectively and wherein the second high control means includes an inverter that includes an input connected to the first input signal and an output connected to the second high switching means and is connected to a power supply and the first high memory point; and

wherein the second high control means is connected to the second high switching means.

2. The output buffer set forth in claim 1 , wherein said second high switching means included in said second offset switching stage, comprise a third P type transistor comprising a gate on which said upstream high control point is applied and is connected to the second high and low control means, and in that if said upstream high control point is less than or equal to said low logical level, said third P type transistor enables switching of said output signal to the high logical level.

3. The output buffer set forth in claim 1 , wherein said second low switching means included in said second offset switching stage, comprise a third N type transistor comprising a gate on which said upstream low control point is applied, and in that if said upstream low control point is greater than or equal to said high logical level, said third N type transistor enables switching of said output signal to the low logical level.

4. The output buffer set forth in claim 1 and further comprising at least a third offset switching stage placed downstream from said second offset switching stage and comprising identical components to said second offset switching stage, each offset switching stage placed downstream from another offset switching stage providing additional downstream high and low control points delayed in time with respect to said upstream high and low control points respectively, generated in said upstream offset switching stage.

5. The output buffer set forth in claim 1 , wherein said first high and low control means included in said first switching stage, each comprise at least one inverter.

6. Output buffer into which first and second input signals are applied and that delivers an output signal, the output signal being switchable between a high logical level and a low logical level, and vice versa, the output buffer comprising:

a first switching stage, which comprises:

a first high switch to switch the output signal from the low logical level to the high logical level;

first low switch to switch the output signal from the high logical level to the low logical level;

first high and low control circuit acting on the first high and low switches, respectively, the first high and low control circuits receiving the first and second input signals, respectively; and

first high and low memory points,

the output from the first high control circuit and the input to the first high switch being connected to the first high memory point, the first high memory point further connected to the first low control circuit and to a second high control circuit,

the output from the first low control circuit and the input to the first low switch being connected to the first low memory point, the first low memory point further connected to the first high control circuit and to a second low control circuit; and

a second offset switching stage installed in cascade downstream from the first switching stage and comprising:

a second high switch to switch the output signal;

a second low switch to switch the output signal; and

second high and low control circuits acting on the second high and low switches respectively, through upstream high and low control points respectively, the second high and low control circuits receiving the first and second input signals respectively, the upstream high and low control points being delayed in time with respect to the high and low memory points, and wherein the second high control circuit includes an inverter that includes an input connected to the first input signal and an output connected to the second high switch and is connected to a power supply and the first high memory point; and

wherein the second high control circuit is connected to the second high switch.

7. The output buffer set forth in claim 6 , wherein said second high switch included in said second offset switching stage, comprises a third P type transistor comprising a gate on which said upstream high control point is applied, and in that if said upstream high control point is less than or equal to said low logical level, said third P type transistor enables switching of said output signal to the high logical level.

8. The output buffer set forth in claim 6 , wherein said second low switch included in said second offset switching stage, comprises a third N type transistor comprising a gate on which said upstream low control point is applied, and in that if said upstream low control point is greater than or equal to said high logical level, said third N type transistor enables switching of said output signal to the low logical level.

9. The output buffer set forth in claim 6 and further comprising at least a third offset switching stage placed downstream from said second offset switching stage and comprising identical components to said second offset switching stage, each offset switching stage placed downstream from another offset switching stage providing additional downstream high and low control points delayed in time with respect to said upstream high and low control points respectively, generated in said upstream offset switching stage.

10. The output buffer set forth in claim 6 , wherein said first high and low control circuits included in said first switching stage, each comprises at least one inverter.

11. An electronic circuit comprising an output buffer into which first and second input signals are applied and that delivers an output signal, the output signal being switchable between a high logical level and a low logical level, and vice versa, wherein the output buffer comprises:

a first switching stage, which comprises:

a first high switch to switch the output signal from the low logical level to the high logical level;

first low switch to switch the output signal from the high logical level to the low logical level;

first high and low control circuit acting on the first high and low switches, respectively, the first high and low control circuits receiving the first and second input signals, respectively; and

first high and low memory points,

the output from the first high control circuit and the input to the first high switch being connected to the high memory point, the first high memory point further connected to the first low control circuit and to a second high control circuit,

the output from the first low control circuit and the input to the first low switch being connected to the low memory point, the first low memory point further connected to the first high control circuit and to a second low control circuit; and

a second offset switching stage installed in cascade downstream from the first switching stage and comprising:

a second high switch to switch the output signal;

a second low switch to switch the output signal; and

second high and low control circuits acting on the second high and low switches respectively, through upstream high and low control points respectively, the second high and low control circuits receiving the first and second input signals respectively, the upstream high and low control points being delayed in time with respect to the high and low memory points, respectively and wherein the second high control circuit includes an inverter that includes an input connected to the first input signal and an output connected to the second high switch and is connected to a power supply and the first high memory point; and

wherein the second high control circuit is connected to the second high switch.

12. An output buffer comprising:

first and second input signals, the first and second input signals switchable between a high logical level and a low logical level;

a first switching stage comprising:

a first high control circuit configured to receive the first input signal and output a first control signal;

a first low control circuit configured to receive the second input signal and output a second control signal;

a first high switch configured to receive the output of the first high control circuit and switch the logical level of the first control signal;

a first low switch configured to receive the output of the first low control circuit and switch the logical level of the second control signal;

a first high memory point connected between the output of the first high control circuit and the input of the first high switch; and

a second high memory point connected between the output of the first low control circuit and the input of the first low switch; and

a second offset switching stage comprising:

a second high control circuit configured to receive the first input signal and, after a latency period, output a third control signal, and wherein the second high control circuit includes an inverter that includes an input connected to the first input signal and an output connected to a second high switch and is connected to a power supply and the first high memory point;

a second low control circuit configured to receive the second input signal and, after a latency period, output a fourth control signal;

the second high switch configured to receive the output of the second high control circuit and switch the logical level of the third control signal, wherein the second high switch is connected to the second high control circuit;

a second low switch configured to receive the output of the second low control circuit and switch the logical level of the fourth control signal;

a first high control point connected between the output of the second high control circuit and the input of the second high switch, the first high control point time-delayed with respect to the first high memory point; and

a first low control point connected between the output of the second low control circuit and the input of the second low switch, the first low control point time-delayed with respect to the first low memory point.

13. The output buffer of claim 12 , wherein the first and second high and low control circuits each comprise an N-channel transistor and a P-channel transistor.

14. The output buffer of claim 13 , further comprising:

the first high memory point connected to the source of the P-channel transistor of the first low control circuit and to the source of the N-channel transistor of the second high control circuit; and

the first low memory point connected to the source of the N-channel transistor of the first high control circuit and to the source of the P-channel transistor of the second low control circuit.

15. The output buffer of claim 12 , further comprising:

a third offset switching stage comprising:

a third high control circuit configured to receive the first input signal and, after a latency period, output a fifth control signal;

a third low control circuit configured to receive the second input signal and, after a latency period, output a sixth control signal;

a third high switch configured to receive the output of the third high control circuit and switch the logical level of the fifth control signal;

a third low switch configured to receive the output of the third low control circuit and switch the logical level of the sixth control signal;

a second high control point connected between the output of the third high control circuit and the input of the third high switch, the second high control point time-delayed with respect to the first high control point; and

a second high control point connected between the output of the third low control circuit and the input of the third low switch, the second low control point time-delayed with respect to the first low control point.

16. The output buffer of claim 15 , wherein the first, second and third high and low control circuits each comprise an N-channel transistor and a P-channel transistor.

17. The output buffer of claim 16 , further comprising:

the first high memory point connected to the source of the P-channel transistor of the first low control circuit and to the source of the N-channel transistor of the second high control circuit;

the first low memory point connected to the source of the N-channel transistor of the first high control circuit and to the source of the P-channel transistor of the second low control circuit;

the first high control point connected to the source of the N-channel transistor of the third high control circuit; and

the first low control point connected to the source of the P-channel transistor of the third low control circuit.

18. The output buffer of claim 1 , wherein the second high control means is not connected to output signal.

Assignments (11)