Granted Patent B2

US 8,015,345 · App. 11/787,101 · Granted Sep 6, 2011

Abstract

Claims (36)

1. A method for accessing a programmable memory having a two-level mode and a multilevel mode and accessible with at least two reading modes, said programmable memory including memory regions being organized into pages including a sub-group of memory cells for storing error correction codes of data stored in the multilevel mode, comprising:

providing, for a page, at least one first cell storing error correction code indicating whether error correction code for the page is to be stored;

providing, in said sub-group of cells, at least one second cell to store information concerning a programmed or erased state of the page; and

reading the content of the first and of the second cell before accessing, to programming the page.

2. The method according to claim 1 , wherein said first cell is part of the first page of the region and said second cell is a cell being part of said sub-group of cells for the error correction in the multilevel mode.

3. The method according to claim 2 , wherein the programming step of a page first provides at least the programming of said first or second cell.

4. A method for accessing data stored in an electronic memory device comprising:

for a page of memory, storing in at least one memory cell in the page, error correction code data indicating whether error correction code information for the page is to be stored;

for said page of memory, storing in at least one memory cell in the page, erase guard data indicating a programmed or erased state of the page; and

prior to accessing data stored in each page of memory, reading the page error correction and page erase guard data for that page.

5. The method of claim 4 wherein the memory cells in some of the pages are multilevel storage cells storing two or more bits of data and some of the memory cells store a single bit of data.

6. The method of claim 4 wherein the erase guard data and error correction code data defining three possible states for a region of the memory corresponding to a plurality of pages of memory, the three states being an erased state, a two bits per cell state, and a one bit per cell state, and wherein the error correction code data is utilized in the erased state and the two bits per cell state.

7. The method of claim 4 wherein each of the memory cells comprises a FLASH memory cell.

8. The method of claim 4 wherein the accessing data stored in each page of memory comprises programming data in such memory cells in the page and erasing the data stored in such memory cells in the page.

9. A memory device, comprising:

a memory-cell array including,

at least one group of memory cells divided into programmable memory regions with two different data storage densities,

each programmable memory region including memory cells arranged in rows and columns with memory cells in respective rows being designated pages,

each page including a subgroup of memory cells operable to store error correction code data associated with data stored in the other memory cells in that page,

wherein each page includes at least one memory cell operable to store error correction code guard data indicating whether error correction coding is applied to data stored in the memory cells of that page, and

wherein the subgroup of memory cells in each page stores erase guard data indicating a programmed or erased state of the data stored in the memory cells of that page.

10. The memory device of claim 9 wherein each of the memory cells in the memory cell array comprises a FLASH memory cell.

11. The memory device of claim 9 further comprising sensing and data correction circuitry coupled to the memory-cell array and operable to utilize the error correction code guard data and erase guard data when accessing data stored in the pages.

12. The memory device of claim 9 wherein the memory cells in some of the pages are multilevel storage cells storing two or more bits of data and some of the memory cells store a single bit of data.

13. The memory device of claim 9 wherein the erase guard data and error correction code data define three possible states for each region of the memory, the three states being an erased state, a two bits per cell state, and a one bit per cell state, and wherein the error correction code data is utilized in the erased state and the two bits per cell state.

14. An electronic system, comprising:

electronic circuitry;

a memory device coupled to the electronic circuitry, the memory device including,

a memory-cell array including,

at least one group of memory cells divided into programmable memory regions with two different data storage densities,

each programmable memory region including memory cells arranged in rows and columns with memory cells in respective rows being designated pages,

each page including a subgroup of memory cells operable to store error correction code data associated with data stored in the other memory cells in that page,

wherein each page includes at least one memory cell operable to store error correction code guard data indicating whether error correction coding is applied to data stored in the memory cells of that page, and

wherein the subgroup of memory cells in each page stores erase guard data indicating a programmed or erased state of the data stored in the memory cells of that page.

15. The electronic system of claim 14 wherein the memory cells comprise FLASH memory cells.

16. The electronic system of claim 14 wherein the electronic circuitry comprises computer system, cellular telephone, personal digital assistant, or memory stick circuitry.

Assignments (11)