IP Library Granted Patent US 7,541,669
Granted Patent B2
US 7,541,669 · App. 11/788,346 · Granted Jun 2, 2009

Semiconductor device package with base features to reduce leakage

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Quick Facts
Patent No.
US 7,541,669
App. No.
11/788,346
Granted
Jun 2, 2009
Kind
B2
Abstract

A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Claims (31)

1. A semiconductor device package comprising:

a container including a base and sidewalls, said base configured to support a semiconductor device chip, said base and sidewalls comprising materials having different thermal expansion coefficients, and

a lead frame extending through at least one of said sidewalls, characterized in that said base has at least one reentrant feature that is positioned within the thickness of at least one of said sidewalls and engages said at least one sidewall, wherein the at least one reentrant feature is a hook-like flange that engages a reciprocal feature of the at least one sidewall to inhibit lateral separation of the at least one sidewall from the base.

2. The package of claim 1 , wherein said reentrant feature is located at the side and near the top of said base.

3. The package of claim 1 , further including at least one conductor electrically coupling said lead frame to said chip, and an encapsulant covering said chip and said conductor.

4. A semiconductor device package comprising:

a container including a base and sidewalls, said base configured to support a semiconductor device chip, said base and sidewalls comprising materials having different thermal expansion coefficients, and

a lead frame extending through at least one of said sidewalls, characterized in that said base has at least one groove that is positioned within the thickness of at least one of said sidewalls and engages said at least one sidewall, wherein:

the at least one groove is defined by a recess between two plateau regions of substantially equal height on a top surface of the base;

the at least one sidewall has a reciprocal protrusion in a bottom-facing surface of the at least one sidewall; and

the recess defining the at least one groove in the base receives the reciprocal protrusion of the at least one sidewall.

5. The package of claim 4 , wherein said groove has sharp corners at the top of said base.

6. The package of claim 4 , further including at least one conductor electrically coupling said lead frame to said chip, and an encapsulant covering said chip and said conductor.

7. The package of claim 1 , wherein the at least one reentrant feature is continuous along at least one edge of the base mating with the at least one sidewall.

8. The package of claim 1 , wherein the at least one reentrant feature is segmented along at least one edge of the base to form teeth mating with the at least one sidewall.

9. The package of claim 1 , wherein the base further comprises at least one groove that is positioned within the thickness of at least one of said sidewalls and engages said at least one sidewall.

10. A base for supporting a semiconductor device chip in a semiconductor device package, wherein:

the base comprises a plurality of outer edges adapted to mate with sidewalls of the semiconductor device package;

the base has at least one reentrant feature that is adapted to be positioned within the thickness of at least one of said sidewalls and to engage said at least one sidewall, wherein the at least one reentrant feature is a hook-like flange that engages a reciprocal feature of the at least one sidewall to inhibit lateral separation of the at least one sidewall from the base.

11. The base of claim 10 , wherein the at least one reentrant feature is continuous along each edge of the base adapted to mate with one of the sidewalls.

12. The base of claim 10 , wherein the at least one reentrant feature is segmented along at least one edge of the base to form teeth adapted to mate with said at least one sidewall.

13. The base of claim 10 , wherein the base further comprises at least one groove that is positioned within the thickness of at least one of said sidewalls and engages said at least one sidewall.

14. The base of claim 10 , wherein the base and the sidewalls comprise materials having different thermal expansion coefficients.

15. The base of claim 13 , wherein:

the at least one groove is defined by a recess between two plateau regions of substantially equal height on a top surface of the base;

the at least one sidewall has a reciprocal protrusion in a bottom-facing surface of the at least one sidewall; and

the recess defining the at least one groove in the base receives the reciprocal protrusion of the at least one sidewall.

16. The package of claim 9 , wherein:

the at least one groove is defined by a recess between two plateau regions of substantially equal height on a top surface of the base;

the at least one sidewall has a reciprocal protrusion in a bottom-facing surface of the at least one sidewall; and

the recess defining the at least one groove in the base receives the reciprocal protrusion of the at least one sidewall.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2007
From: CARBERRY, PATRICK JOSEPH; GILBERT, JEFFERY JOHN; LIBRICZ, GEORGE JOHN, JR.; MOYER, RALPH SALVATORE; OSENBACH, JOHN WILLIAM; SAFAR, HUGO FERNANDO; SHILLING, THOMAS HERBERT
To: AGERE SYSTEMS INC.
Reel/Frame 020257/0237 →