Method of controlled low-k via etch for Cu interconnections
View Patent ↗An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.
1. A method for the formation of straight sidewall vias comprising the steps of:
providing an interconnect stack having a substrate, at least one metal interconnect formed therein, an etch stop layer, a transition layer, an interlayer dielectric (ILD) layer and a photoresist;
etching a portion of the ILD layer to a predetermined point to form a via having a first depth and an unetched portion of the ILD layer between the first depth and the transition layer;
converting the unetched portion of ILD layer in the via to an oxide-like material by ashing the interconnect stack; and
wet etching the via through the transition layer to remove the oxide-like material, wherein the etch stop layer remains substantially unaffected and the sidewalls of the via are straight.
2. The method of claim 1 , wherein the etching utilizes a carbon-fluorine species.
3. The method of claim 1 , wherein the ashing utilizes an oxygenated material.
4. The method of claim 1 , wherein the etching step forms a polymer on the sidewalls of the via in the portion where the ILD layer is etched away.
5. The method of claim 4 , wherein the ashing releases residual carbon-fluorine absorbed into the ILD layer during etching.
6. The method of claim 4 , wherein the ashing substantially removes the polymer formed on sidewalls of the via.
7. The method of claim 4 , wherein the ashing depletes carbon in the unetched portion of the ILD layer.
8. The method of claim 7 , wherein the depletion of carbon modifies the unetched portion of the ILD layer into an carbon depleted oxide material.
9. The method of claim 8 , wherein the ashing forms a superficial oxide layer on the sidewalls of the via.
10. The method of claim 8 , wherein the wet etching removes the superficial oxide layer on the sidewalls, the carbon depleted oxide material, and a portion of the transition layer.
11. The method of claim 10 , further comprising a step of removing a portion of the etch stop layer to expose a Cu interconnect.
12. The method of claim 1 , wherein the substrate is an ILD layer.
13. The method of claim 1 , wherein the etch stop layer is SiCN.
14. The method of claim 13 , wherein the SiCN etch stop layer is in the range of 250-500 Å.
15. The method of claim 1 , wherein the ashing step utilizes an oxygenated material selected from the group consisting of O 2 , CO 2 , and CO.
16. The method of claim 1 , wherein the wet etching material is HF.
17. The method of claim 1 , wherein the ILD layer has a k value of ≦2.5.