Semiconductor device having a circular-arc profile on a silicon surface
View Patent ↗A semiconductor device includes a shallow isolation trench (STI) structure on a silicon substrate for isolating element-forming regions from one another. The surface region of the silicon substrate in the element-forming regions, as viewed in the extending direction of the gate electrode lines, once falls and thereafter rises monotonically from the periphery toward the center of the element-forming regions.
1. A semiconductor device, comprising:
a silicon substrate;
an element isolation region including a trench formed in said silicon substrate and an insulation film formed within said trench;
a plurality of element-forming regions configured by a surface region of said silicon substrate and isolated from one another by said element isolation region; and
a gate electrode line extending on said element isolation region and said element-forming regions,
wherein said surface region of said silicon substrate in said element-forming regions includes a height profile as viewed in a direction along said gate electrode line, said height profile being such that said surface region falls in each of the element-forming regions near the trench and thereafter rises monotonically and continuously as viewed from a boundary between said element-forming regions and said element isolation region to a center of said each of the element-forming regions.
2. The semiconductor device according to claim 1 , wherein said height profile is such that a height of a center of said surface region is equal to a height of a periphery of said surface region.
3. The semiconductor device according to claim 1 , wherein a portion of said surface region that includes a center of the surface region has a shape of a circular arc.
4. The semiconductor device according to claim 1 , further comprising:
a contact plug in contact with said surface region, said contact plug penetrating a space formed between said gate electrode line and another gate electrode line.
5. The semiconductor device according to claim 4 , wherein a contact layer is interposed between said contact plug and said surface region, said contact layer having a bottom extending between opposing peripheries of said surface region in said element-forming regions.
6. The semiconductor device according to claim 4 , wherein the contact plug contacts the silicon substrate at a curved surface of the center of the surface region.
7. The semiconductor device according to claim 1 , wherein an element-forming region of said element-forming regions extends in a direction slanted from said gate electrode line.
8. The semiconductor device according to claim 1 , wherein a top surface of the insulation film contacts a lower surface of the gate electrode line.
9. The semiconductor device according to claim 1 , wherein the surface region of the silicon substrate comprises a gate oxide film, the gate oxide film being confined between the trench and another trench.
10. The semiconductor device according to claim 1 , wherein the height profile comprises a first V-shaped profile in a first periphery of the surface region, a second V-shaped profile in a second periphery of the surface region, and a circular-arc shape profile in a center of the surface region, the circular-arc shape profile extending from the first V-shaped profile to the second V-shaped profile.
11. The semiconductor device according to claim 10 , wherein a height of a highest portion of the first V-shaped profile, a highest portion of the second V-shaped profile, and a height of a highest portion of the circular-arc shape profile are equal to the height of a top surface of the insulation film.
12. The semiconductor device according to claim 11 , wherein the height profile is confined between the trench and another trench, the first V-shaped profile extending from the trench and the second V-shaped profile extending from the another trench.
13. The semiconductor device according to claim 1 , wherein impurities introduced to exposed surface portions of the silicon substrate which are exposed from the gate electrode line and another gate electrode line, parallel to the gate electrode line, form source regions and drain regions in the element-forming regions, the gate electrode line and the another gate electrode line intersecting with one of the element-forming regions.
14. The semiconductor device according to claim 13 , wherein one of the source regions and one of the drain regions, formed on one of the exposed surface portions of the silicon substrate at opposite sides of the gate electrode line, are included in a single metal oxide semiconductor (MOS) transistor.
15. The semiconductor device according to claim 14 , wherein a rhombus-shaped region, defined by a portion of the gate electrode line and a portion of the element-forming regions overlapping one another, forms a channel region of the MOS transistor that extends between the one of the source regions and the one of the drain regions.
16. The semiconductor device according to claim 15 , wherein a length of the channel region along a direction perpendicular to an extending direction of the gate electrode is equal to a line space between the gate electrode line and the another gate electrode line.
17. The semiconductor device according to claim 1 , wherein the height profile is such that a height of a center of the surface region is equal to a height of a top surface of the insulation film.
18. A semiconductor device, comprising:
a silicon substrate;
an element isolation region including a trench formed in the silicon substrate and an insulation film formed within the trench;
a plurality of element-forming regions configured by a surface region of the silicon substrate and isolated from one another by the element isolation region; and
a gate electrode line extending on the element isolation region and the element-forming regions,
wherein the surface region of the silicon substrate in the element-forming regions has a height profile as viewed in a direction along the gate electrode line, and
wherein the height profile comprises a first V-shaped profile in a first periphery of the surface region, a second V-shaped profile in a second periphery of the surface region, and a circular-arc shape profile in the center of the surface region, the circular-arc shape profile extending from the first V-shaped profile to the second V-shaped profile,
wherein a top surface of the insulation film abuts a lower surface of the gate electrode line.
19. The semiconductor device according to claim 18 , wherein the surface region of the silicon substrate comprises a gate oxide film, the gate oxide film being confined between the trench and another trench, and
wherein an element-forming region of said element-forming regions extends in a direction slanted from said gate electrode line.
20. The semiconductor device according to claim 18 , wherein impurities introduced to exposed surface portions of the silicon substrate which are exposed from the gate electrode line and another gate electrode line, parallel to the gate electrode line, form source regions and drain regions in the element-forming regions, the gate electrode line and the another gate electrode line intersecting with one of the element-forming regions,
wherein one of the source regions and one of the drain regions formed on one of the exposed surface portions of the silicon substrate at opposite sides of the gate electrode line are included in a single metal oxide semiconductor (MOS) transistor,
wherein a rhombus-shaped region, defined by a portion of the gate electrode line and a portion of the element-forming regions overlapping one another, forms a channel region of the MOS transistor that extends between the one of the source regions and the one of the drain regions, and
wherein a length of the channel region along a direction perpendicular to an extending direction of the gate electrode is equal to a line space between the gate electrode line and the another gate electrode line.
21. The semiconductor device according to claim 18 , wherein a height of a highest portion of the first V-shaped profile, a height of a highest portion of the second V-shaped profile, and a height of a highest portion of the circular-arc shape profile are equal to a height of a top surface of the insulation film.
22. A semiconductor device, comprising:
a silicon substrate;
an element isolation region comprising a pair of trenches formed in the silicon substrate and an insulation film formed within the pair of trenches;
a plurality of element-forming regions configured by a surface region of the silicon substrate and isolated from one another by the element isolation region; and
a gate electrode line extending on the element isolation region and the element-forming regions,
wherein the surface region of the silicon substrate in the element-forming regions has a height profile as viewed in a direction along the gate electrode line,
wherein the height profile comprises a first V-shaped profile in a first periphery of the surface region, a second V-shaped profile in a second periphery of the surface region, and a circular-arc shape profile in the center of the surface region, the circular-arc shape profile extending from the first V-shaped profile to the second V-shaped profile,
wherein a height of a highest portion of the first V-shaped profile, a height of a highest portion of the second V-shaped profile, and a height of a highest portion of the circular-arc shape profile are equal with a height of a top surface of the insulation film,
wherein the top surface of the insulating film abuts a lower surface of the gate electrode line, and
wherein the surface region of the silicon substrate comprises a gate oxide film, the gate oxide film being confined between the pair of trenches,
wherein impurities introduced to exposed surface portions of the silicon substrate which are exposed from the gate electrode line and another gate electrode line, parallel to the gate electrode line, form source regions and drain regions in the element-forming regions, the gate electrode line and the another gate electrode line intersecting with one of the element-forming regions,
wherein one of the source regions and one of the drain regions formed on one of the exposed surface portions of the silicon substrate at opposite sides of the gate electrode line form a single metal oxide semiconductor (MOS) transistor,
wherein a rhombus shaped region, defined by a portion of the gate electrode line and a portion of the element-forming regions overlapping one another, forms a channel region of the MOS transistor that extends between the one of the source regions and the one of the drain regions,
wherein a length of the channel region along a direction perpendicular to an extending direction of the gate electrode is equal to a line space between the gate electrode line and the another gate electrode line, and
wherein an element-forming region of said element-forming regions extends in a direction slanted from said gate electrode line.