Semiconductor device and method of manufacturing the same
View Patent ↗Example embodiments are directed to a method of manufacturing a semiconductor device and a semiconductor device including a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an upper surface of the active region.
1. A semiconductor device, comprising:
a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an upper surface of the active region and a sidewall of the groove being apart from the isolation regions;
a gate structure crossing over the plurality of grooves and including a charge storage layer and a control gate, and
a spacer and a pad oxide between the control gate and the isolation regions, wherein the groove extends along a direction perpendicular to a running direction of the gate structure, such that a source and a drain region adjacent to the gate structure have a “U” shape.
2. The semiconductor device of claim 1 , the gate structure including
a tunneling insulation layer between the charge storage layer and the substrate, and,
a blocking insulation layer between the charge storage layer and the control gate.
3. The semiconductor device of claim 1 , wherein the control gate is a multilayer.
4. The semiconductor device of claim 1 , wherein the control gate is a poly or poly to metal layer.
5. The semiconductor device of claim 1 , wherein the spacer and the pad oxide are made of silicon oxide.
6. The semiconductor device of claim 2 , wherein the tunneling insulation layer is made of a material selected from the group consisting of silicon oxide, silicon nitride, aluminum oxide, and hafnium oxide.
7. The semiconductor device of claim 1 , wherein the gate structure includes a charge trap gate structure.
8. The semiconductor device of claim 7 , the charge trap gate structure includes
an ONO layer in each of the plurality of grooves and on each of the plurality of isolation regions, and
a control gate on the ONO layer.
9. The semiconductor device of claim 8 , wherein the ONO layer includes
a first oxide layer in each of the plurality of grooves and on each of the plurality of isolation regions,
a nitride layer on the first oxide layer, and
a second oxide layer on the nitride layer.
10. The semiconductor device of claim 7 , the charge trap gate structure including
a tunnel insulating layer in each of the plurality of grooves and on each of the plurality of isolation regions, and
a charge storage layer on the tunnel insulating layer,
a blocking insulating layer on the charge storage layer, the blocking insulating layer having a second dielectric constant which is greater than the first dielectric constant of the tunnel insulating layer; and
a gate electrode on the blocking insulating layer, wherein the gate electrode includes a metal layer.
11. The semiconductor device of claim 10 , wherein the tunnel insulating layer comprises at least one of silicon oxide, silicon oxynitride, and silicon nitride.
12. The semiconductor device of claim 1 , wherein the charge storage layer comprises at least one of silicon nitride, silicon oxynitride, silicon-rich oxide, metallic oxynitride and other metallic oxide materials.
13. The semiconductor device of claim 10 , wherein the blocking insulating layer comprises a metal oxide doped with a group IV element.
14. The semiconductor device of claim 10 , wherein the blocking insulating layer comprises at least one of HfO 2 , Al 2 O 3 , La 2 O 3 , Hf 1-X Al X O Y , Hf X Si 1-X O 2 , Hf—Si-oxynitride, ZrO 2 , Zr X Si 1-X O 2 , and Zr—Si-oxynitride.
15. The semiconductor device of claim 10 , wherein the gate electrode comprises a metal layer having a work-function of at least 4 eV.
16. The semiconductor device of claim 10 , wherein metal layer is one of titanium, titanium nitride, tantalum nitride, tantalum, tungsten, hafnium, niobium, molybdenum, ruthenium dioxide, molybdenum nitride, iridium, platinum, cobalt, chrome, ruthenium monoxide, titanium aluminide (Ti 3 Al), Ti 2 AlN, palladium, tungsten nitride (WN x ), tungsten silicide (WSi), nickel silicide, or combinations thereof.
17. The semiconductor device of claim 1 , wherein a shape of a bottom portion of each of the plurality of grooves has an obtuse or rounded profile.
18. The semiconductor device of claim 1 , wherein each groove is in a center portion of the active region.
19. A semiconductor device, comprising:
a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an upper surface of the active region;
a gate structure crossing over the plurality of grooves and including a charge storage layer and a control gate; and
a spacer and a pad oxide between the control gate and the isolation regions, wherein major axes of the active regions and major axes of the plurality of grooves are in the same direction, wherein the groove extends along a direction perpendicular to a running direction of the gate structure, such that a source and a drain region adjacent to the gate structure have a “U” shape.
20. The semiconductor device of claim 19 , wherein the plurality of grooves extend along a source, a channel, and a drain.
21. A semiconductor device, comprising:
a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an upper surface of the active region and a sidewall of the groove being apart from the isolation regions;
a gate structure crossing over the plurality of grooves and including a charge storage layer and a control gate, wherein the groove extends along a direction perpendicular to a running direction of the gate structure, such that a source and a drain region adjacent to the gate structure have a “U”-shape, wherein the charge storage layer is formed on an inner surface of the groove and has a substantially uniform thickness; and
a spacer and a pad oxide between the control gate and the isolation regions.
22. The semiconductor device of claim 21 , wherein the gate structure includes
a tunneling insulation layer between the charge storage layer and the substrate, and
a blocking insulation layer between the charge storage layer and the control gate.
23. The semiconductor device of claim 21 , wherein the control gate is a multilayer.
24. The semiconductor device of claim 21 , wherein the control gate is a poly or poly to metal layer.
25. The semiconductor device of claim 21 , wherein the spacer and the pad oxide are made of silicon oxide.
26. The semiconductor device of claim 22 , wherein the tunneling insulation layer is made of a material selected from the group consisting of silicon oxide, silicon nitride, aluminum oxide, and hafnium oxide.
27. The semiconductor device of claim 21 , wherein the gate structure includes a charge trap gate structure.
28. The semiconductor device of claim 27 , wherein the charge trap gate structure includes
an ONO layer in each of the plurality of grooves and on each of the plurality of isolation regions, and
a control gate on the ONO layer.
29. The semiconductor device of claim 28 , wherein the ONO layer includes
a first oxide layer in each of the plurality of grooves and on each of the plurality of isolation regions,
a nitride layer on the first oxide layer, and
a second oxide layer on the nitride layer.
30. The semiconductor device of claim 27 , wherein the charge trap gate structure includes
a tunnel insulating layer in each of the plurality of grooves and on each of the plurality of isolation regions,
a charge storage layer on the tunnel insulating layer,
a blocking insulating layer on the charge storage layer, the blocking insulating layer having a second dielectric constant which is greater than the first dielectric constant of the tunnel insulating layer; and
a gate electrode on the blocking insulating layer, wherein the gate electrode includes a metal layer.
31. The semiconductor device of claim 30 , wherein the tunnel insulating layer includes at least one of silicon oxide, silicon oxynitride, and silicon nitride.
32. The semiconductor device of claim 21 , wherein the charge storage layer includes at least one of silicon nitride, silicon oxynitride, silicon-rich oxide, metallic oxynitride, and metallic oxide.
33. The semiconductor device of claim 30 , wherein the blocking insulating layer includes a metal oxide doped with a group IV element.
34. The semiconductor device of claim 30 , wherein the blocking insulating layer includes at least one of HfO 2 , Al 2 O 3 , La 2 O 3 , Hf 1-X Al X O Y , Hf X Si 1-X O 2 , Hf—Si-oxynitride, ZrO 2 , Zr X Si 1-X O 2 , and Zr—Si-oxynitride.
35. The semiconductor device of claim 30 , wherein the gate electrode includes a metal layer having a work-function of at least 4 eV.
36. The semiconductor device of claim 30 , wherein metal layer is one of titanium, titanium nitride, tantalum nitride, tantalum, tungsten, hafnium, niobium, molybdenum, ruthenium dioxide, molybdenum nitride, iridium, platinum, cobalt, chrome, ruthenium monoxide, titanium aluminide(Ti 3 Al), Ti 2 AlN, palladium, tungsten nitride(WN x ), tungsten silicide (WSi), nickel silicide, or combinations thereof.
37. The semiconductor device of claim 21 , wherein a shape of a bottom portion of each of the plurality of grooves has an obtuse or rounded profile.
38. The semiconductor device of claim 21 , wherein each groove is in a center portion of the active region.