Memory device with a nonvolatile memory array
View Patent ↗A memory device having a nonvolatile memory array, at least one driver for programming the memory array, which driver is connected to the memory array in order to drive a programming potential, and a drive circuit for controlling the at least one driver, wherein the drive circuit has at least one switch for switching a current as a function of the digital logic potential at the input and the drive circuit has a current-to-voltage converter connected to the output, which converter is designed to output a control potential depending on the switched current for driving the at least one driver.
1. A memory device comprising:
a nonvolatile memory array;
at least one driver for programming the memory array, which driver is connected to the memory array in order to drive a programming potential; and
a drive circuit for controlling the at least one driver, the drive circuit having at least one current source for providing a current,
wherein the drive circuit has at least one switch for switching the current as a function of a digital logic potential at an input, and
wherein the drive circuit has a current-to-voltage converter connected to an output, wherein said current-to-voltage converter outputs a control potential depending on the switched current for driving the at least one driver.
2. The memory device according to claim 1 , wherein the current-to-voltage converter has a current-summing node, and wherein the control potential depends on the potential at the current-summing node.
3. The memory device according to claim 2 , wherein the current-to-voltage converter has a threshold switch that is connected to the current-summing node and to the output of the drive circuit.
4. The memory device according to claim 2 , wherein the current-to-voltage converter has a plurality of current mirrors for mirroring the switched current into the current-summing node.
5. The memory device according to claim 1 , wherein the at least one driver has a push-pull stage.
6. The memory device according claim 1 , wherein a decoder is connected between the drive circuit and the at least one driver.
7. The memory device according to claim 1 , wherein the current-to-voltage converter is connected by a first supply voltage terminal to a first programming potential and by a second supply voltage terminal to a second programming potential.
8. The memory device according to claim 7 , wherein a differential voltage between the first programming potential and the second programming potential corresponds to a logic voltage between a first logic potential and a second logic potential or is set in a manner of such a logic voltage.
9. The memory device according to claim 7 , wherein the first supply voltage terminal and/or the second supply voltage terminal are connected to a variable voltage source.
10. The memory device according to claim 9 , wherein the variable voltage source has a voltage regulator or a controllable charge pump.
11. The memory device according to claim 7 , having a limiter for limiting the current drawn from the first and/or second supply voltage terminal.
12. The memory device according to claim 11 , wherein the limiter for limiting the current draw has at least one constant current source, which outputs the switched current.
13. The memory device according to claim 1 , wherein the drive circuit has connections such that the switched current flows between a logic potential and a programming potential.
14. A memory device comprising:
a nonvolatile memory array;
at least one driver for programming the memory array, which driver is connected to the memory array in order to drive a programming potential; and
a drive circuit for controlling the at least one driver,
wherein the drive circuit has at least one switch for switching a current as a function of a digital logic potential at an input, and
wherein the drive circuit has a current-to-voltage converter connected to an output, wherein said current-to-voltage converter outputs a control potential depending on the switched current for driving the at least one driver, wherein said least drive circuit includes a first drive circuit section, and a second drive circuit section that is complementary to the first drive circuit section, and wherein said first drive circuit section outputs a first positive control potential and said second drive circuit section outputs a second negative control potential, and wherein the first drive circuit section is connected to a PMOS transistor of the driver for driving a positive programming potential, and the second drive circuit section is connected to an NMOS transistor of the driver or driving a negative programming potential.