Semiconductor package with bypass capacitor
View Patent ↗A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.
1. A semiconductor package comprising:
a substrate having upper and lower surfaces and comprising first and second electrical paths, the first and the second electrical paths including first and second through holes, respectively, each of the first and the second through holes electrically connecting between the upper and the lower surfaces of the substrate;
a semiconductor chip mounted on the upper surface and comprising a plurality of pads, the pads including a first pad to be supplied with a power supply and a second pad to be grounded; and
at least one bypass capacitor mounted on the lower surface and comprising first and second terminals, the first and the second terminals being connected to the first and the second pads through the first and the second electrical paths, respectively.
at least one first land formed on said lower surface of said substrate to supply a first power voltage to said first pad; and
at least one second land formed on said lower surface of said substrate to supply a second power voltage to said second pad.
2. The semiconductor package according to claim 1 , wherein the bypass capacitor comprises a chip capacitor.
3. The semiconductor package according to claim 1 , wherein:
the semiconductor chip comprises a surface which has a center area and a peripheral area; and
the pads are arranged only on the center area.
4. The semiconductor package according to claim 1 , wherein the substrate is a two metal layer substrate and comprises a flexible polyimide tape as a base member.
5. The semiconductor package according to claim 1 , wherein the semiconductor chip is a semiconductor memory chip.
6. The semiconductor package according to claim 1 , wherein
said first and second through holes are arranged closer corresponding pads of said plurality of pads in the first and second electrical path than said first land and said second land.
7. A semiconductor package comprising:
a substrate having upper and lower surfaces and comprising first and second electrical paths, the first and the second electrical paths including first and second through holes, respectively, each of the first and the second through holes electrically connecting between the upper and the lower surfaces of the substrate;
a semiconductor chip mounted on the upper surface and comprising a plurality of pads, the pads including a first pad to be supplied with a power supply and a second pad to be grounded; and
at least one bypass capacitor mounted on the lower surface and comprising first and second terminals, the first and the second terminals being connected to the first and the second pads through the first and the second electrical paths, respectively,
wherein:
the substrate is provided with a plurality of ball lands;
the lower surface comprises a first lower area and a second lower area;
the ball lands are arranged on the first lower area;
the bypass capacitor is mounted on the second lower area;
the upper surface of the substrate comprises a first upper area and a second upper area, the first upper area and the second upper area corresponding to the first lower area and the second lower area, respectively;
the substrate is further provided with a plurality of bond leads and at least one conductive island;
the bond leads are arranged on the second upper area and are connected to the pads, respectively;
the bond leads include first and second bond leads corresponding to the first and the second pads, respectively;
the conductive island is formed on the second lower area and is connected to the first through hole;
the first terminal of the bypass capacitor is mounted on and connected to the conductive island;
the first electrical path is formed, in part, of the conductive island and the first bond lead; and
the second electrical path is formed, in part, of the second bond.
8. The semiconductor package according to claim 7 , wherein:
the substrate is further provided with a ground plane electrode;
the ground plane electrode is formed on the lower surface and is connected to the second through hole;
the ground plane electrode is formed with a window which is positioned on the second lower area;
the conductive island is positioned in the window and is separated from the ground plane electrode; and
the second terminal of the bypass capacitor is mounted on and connected to the ground plane electrode.
9. The semiconductor package according to claim 7 , wherein the conductive island is one or more in number and has a total area less than 15% of the second lower area.
10. The semiconductor package according to claim 7 , wherein:
the substrate is further provided with an additional conductive island;
the additional conductive island is formed on the second lower area and is connected to the second through hole; and
the second terminal of the bypass capacitor is mounted on and connected to the additional conductive island.
11. The semiconductor package according to claim 10 , wherein:
the substrate is further provided with a ground plane electrode;
the ground plane electrode is formed on the lower surface and is formed with first and second windows both of which are positioned on the second lower area; and
the conductive island and the additional conductive islands are positioned in the first and the second windows, respectively, and are separated from the ground plane electrode.
12. The semiconductor package according to claim 10 , wherein the conductive island is one or more in number; the additional conductive island is one or more in number; and the conductive island and the additional conductive island have a total area less than 15% of the second lower area.
13. The semiconductor package according to claim 7 , wherein:
the substrate is further provided with first and second conductive traces;
the first and the second conductive traces are formed on the upper surface;
the first conductive trace is connected to the first bond lead and to the first through hole and constitutes a part of the first electrical path; and
the second conductive trace is connected to the second bond lead and to the second through hole and constitutes a part of the second electrical path.
14. The semiconductor package according to claim 7 , wherein the first and the second bond leads are directly connected to the first and the second through holes, respectively.
15. The semiconductor package according to claim 7 , wherein:
the bond leads are arranged in a predetermined direction; and
the bypass capacitor has a longitudinal direction parallel to the predetermined direction.
16. The semiconductor package according to claim 7 , wherein:
the bond leads are arranged in a predetermined direction; and
the bypass capacitor has a longitudinal direction perpendicular to the predetermined direction.
17. The semiconductor package according to claim 7 , further comprising a plurality of flip chip bumps, which connect between the pads of the semiconductor chip and the bond leads of the substrate, respectively.