Self reference sensing system and method
A self sensing reference system and method are described. The self sensing reference systems and methods facilitate efficient accurate access to information. In one embodiment, a self sensing reference system includes a main cascode component, a self referencing component, and a comparison verification component. The main cascode component receives input on a first current value and a second current value. The self referencing component establishes a plurality of data indications wherein a first data indication is established based upon a comparison of the first current value to the second current value. A comparison verification component verifies a second data indication.
1 . A self reference sensing system comprising:
a main cascode component for receiving input on a first current value and a second current value;
a self referencing component for establishing a plurality of data indications wherein a first data indication is established based upon a comparison of said first current value to said second current value; and
a comparison verification component for verifying a second data indication.
2 . A self reference sensing system of claim 1 wherein said first data indication includes a first logical 0 bit and a second logical 1 bit.
3 . A self reference sensing system of claim 1 wherein said first data indication includes a first logical 1 bit and a second logical 0 bit.
4 . A self reference sensing system of claim 1 wherein said second data indication includes a first logical 1 bit and a second logical 1 bit.
5 . A self reference sensing system of claim 1 wherein said self referencing component includes a first current mirror and a second current mirror.
6 . A self reference sensing system of claim 1 wherein said self referencing component forwards a data indication of a first logical 1 bit and a second logical 0 bit if said first current value plus a first reference value in a first cycle is greater than said second current value and said first current value is greater than said second current value plus said first reference value.
7 . The self reference sensing system of claim 1 wherein said self referencing component forwards a data indication of a first logical 0 bit and a second logical 1 bit if said first current value plus a first reference value is less than said second current value and said first current value is less than said second current value plus said first reference value.
8 . The self reference sensing system of claim 1 wherein said self referencing component forwards a data indication of a first logical 1 bit and a second logical 1 bit if said first current value plus a first reference value is greater than said second current value and said first current value is less than said second current value plus said first reference value.
9 . The self reference sensing system of claim 1 wherein said self referencing component forwards a data indication of a first logical 0 bit and a second logical 0 bit if said first current value plus a first reference value is greater than said second current value and said first current value is less than said second current value plus said first reference value and a verification component verifies said first current value is greater than said second reference value and said second current value is greater than said second reference value.
10 . The self reference sensing system of claim 1 wherein said main cascode component includes a sensing component for sensing current from a memory cell.
11 . A self reference sensing method comprising:
receiving a first current value and a second current value;
forwarding a first logical state indication for a first bit and a first logical state for a second bit if both said first current and said second current are greater than a first reference current;
forwarding a second logical state indication for a first bit and a second logical state for a second bit if an absolute value of the delta of said first current value and said second current value are less than a second reference current;
forwarding a first logical state indication for a first bit and a second logical state indication for a second bit if said first current value is greater than said second current value; and
forwarding a second logical state indication for a first bit and a first logical state indication for a second bit if said first current value is not greater than said second current value.
12 . A self reference sensing method of claim 11 further comprising comparing said first current and said second current.
13 . A self reference sensing method of claim 11 wherein said first current and said second current come from a memory cell.
14 . A self reference sensing method of claim 11 wherein said first current value is associated with a normal current and said second current value is associated with a complimentary current.
15 . A self reference sensing method of claim 11 wherein said first logic state indication is a logical 1.
16 . A self reference sensing method of claim 11 wherein said second logic state indication is a logical 0.
17 . A memory system comprising:
a memory cell for storing data; and
a self reference sensing system for sensing said data.
18 . A self reference sensing method of claim 1 wherein said self reference sensing system determines a data indication value based upon a comparison of a normal current value from said memory cell and a complimentary current value from said memory cell.
19 . A self reference sensing method of claim 1 wherein said memory cell includes a floating gate transistor.