Granted Patent B2

US 7,576,389 · App. 11/808,163 · Granted Aug 18, 2009

Abstract

Claims (37)

1. A semiconductor device having a trench gate transistor comprising:

a groove formed in a semiconductor substrate;

a first gate electrode formed in a lower part of the groove with a gate insulation film interposed between the first gate electrode and the semiconductor substrate;

side walls which are provided on inner walls in an upper part of the groove located at a position higher than the first gate electrode and which have a bottom area larger than a top area thereof;

a second gate electrode formed so as to be in contact with the side walls and a part of the top surface of the first gate electrode;

a first diffusion layer which has a first impurity concentration, which is formed on opposite sides of said trench gate transistor, and which has a bottom portion higher than a top portion of said first gate electrode; and

a second diffusion layer which has a second impurity concentration higher than the first impurity concentration, which is formed next to said first diffusion layer, and which has a bottom portion higher than a bottom portion of said first gate electrode.

2. The semiconductor device according to claim 1 , wherein the side walls are formed along groove inner walls between the top surface of the first gate electrode and the substrate surface.

3. The semiconductor device according to claim 1 , wherein the first gate electrode is formed of a silicon film doped with an impurity.

4. The semiconductor device according to claim 1 , wherein the second gate electrode is formed of a conductive film including at least any one of a silicon film, a silicide film, a metal film, and a metal nitride film.

5. The semiconductor device according to claim 1 , wherein the side walls are formed of an insulation film including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

6. The semiconductor device according to claim 1 , wherein the semiconductor device is a dynamic random access memory having the trench gate transistor used as a transfer gate transistor of a memory cell.

7. The semiconductor device according to claim 1 , further comprising:

a metal contact plug formed on opposite sides of the trench gate transistor, the metal contact plug being in direct contact with the semiconductor substrate.

8. The semiconductor device according to claim 1 , wherein the first gate electrode is formed in a lower region of the groove defining a channel of the trench gate transistor.

9. The semiconductor device according to claim 8 , wherein the top surface of the first gate electrode is located lower than the bottom surface of an impurity diffusion layer on the substrate interface and higher than the distal end of a depletion layer formed in extension from the impurity diffusion layer.

10. A manufacture method of a semiconductor device having a trench gate transistor comprising:

forming a groove in a semiconductor substrate;

forming a gate insulation film in the inside of the groove and on the semiconductor substrate;

forming a first gate electrode in a lower part of the groove;

forming side walls on the groove inner walls at a location higher than the first gate electrode, the side walls having a bottom area larger than a top area thereof;

forming a second gate electrode so as to be in contact with the side walls and a part of the top surface of the first gate electrode;

forming a first diffusion layer which has a first impurity concentration, which is formed on opposite sides of said trench gate transistor, and which has a bottom portion higher than a top portion of said first gate electrode; and

forming a second diffusion layer which has a second impurity concentration higher than the first impurity concentration, and which has a bottom portion higher than a bottom portion of said first gate electrode.

11. The manufacture method of a semiconductor device according to claim 10 , wherein the second gate electrode is formed of a conductive film including at least one of a silicon film, a silicide film, a metal film, and a metal nitride film.

12. The manufacture method of a semiconductor device according to claim 10 , wherein the side walls are formed on an insulation film including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

13. The manufacture method of a semiconductor device according to claim 10 , wherein, in the step of forming the first gate electrode, a conductive film defining the electrode is etched away to leave a predetermined thickness of the film in the groove.

14. The manufacture method of a semiconductor device according to claim 13 , wherein the first gate electrode is formed of a silicon film doped with an impurity.

15. The manufacture method of a semiconductor device according to claim 10 , wherein the step of forming a first gate electrode comprises the steps of:

depositing a gate oxide film on the groove;

depositing a first gate conductive film with an impurity on the gate oxide film;

coating a resist film on the first gate conductive film;

selectively patterning the resist film;

selectively and partially etching the first gate conductive film by plasma dry etching while leaving the resist film on a peripheral region.

16. The manufacture method of a semiconductor device according to claim 15 , wherein the step of forming side walls on the groove inner walls comprises the steps of:

forming an insulation film including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film on the semiconductor substrate, to thereby form an groove side wall film; and

subjecting the groove side wall film to anisotropic dry etching by RIE, to thereby form the groove side walls on upper inner walls of the groove where the first gate electrode is not formed.

Assignments (9)