Reticle, semiconductor die and method of manufacturing semiconductor device
View Patent ↗The invention is directed to increasing the number of semiconductor dice obtained from one semiconductor wafer and enhancing the reliability and yield of the semiconductor dice when the semiconductor dice as products and TEG dice are formed on the semiconductor wafer. TEG die pattern regions are respectively placed on the top and bottom placing a plurality of semiconductor die pattern regions regularly arrayed in a longitudinal direction therebetween. The vertical length of each of the TEG die pattern regions is substantially half of the vertical length of the semiconductor die pattern region. With this reticle, two adjacent TEG die patterns respectively formed by two continuous exposure processes form the area of one semiconductor die pattern. In this manner, the area of the TEG die patterns on the semiconductor wafer is reduced and the yield of the semiconductor dice is increased correspondingly.
1. A reticle comprising:
a group of semiconductor die pattern regions that are elongated in a first direction and are juxtaposed in a second direction so that the first direction is normal to the second direction;
a first test element group die region elongated in the first direction; and
a second test element group die region elongated in the first direction,
wherein the group of the semiconductor die pattern regions is disposed between the first and second test element group die regions, and
a sum of a width of the first test element group die region in the second direction and a width of the second test element group die region in the second direction is equal to a width of one of the semiconductor die pattern regions in the second direction.
2. The reticle of claim 1 , wherein the width of the first test element group die region in the second direction is half of the width of one of the semiconductor die pattern regions in the second direction.
3. The reticle of claim 1 , wherein the first and second test element group die regions comprise alignment measuring regions for preventing misalignment between the reticle and a semiconductor wafer, and the alignment measuring regions are placed in four corners of the reticle.
4. The reticle of claim 1 , wherein the first and second test element group die regions comprise line width measuring regions, and the line width measuring regions are placed in four corners of the reticle.
5. A method of manufacturing a semiconductor device, comprising:
providing a reticle comprising,
a group of semiconductor die pattern regions that are elongated in a first direction and are juxtaposed in a second direction so that the first direction is normal to the second direction,
a first test element group die region elongated in the first direction, and
a second test element group die region elongated in the first direction,
wherein the group of the semiconductor die pattern regions is disposed between the first and second element group die regions, and
a sum of a width of the first test element group die region in the second direction and a width of the second test element group die region in the second direction is equal to a width of one of the semiconductor die pattern regions in the second direction;
performing a first exposure using the reticle to transfer patterns of the reticle onto a semiconductor wafer; and
performing a second exposure using the reticle to transfer the patterns of the reticle onto the semiconductor wafer,
wherein the second exposure is performed by controlling an alignment between a pattern transferred from the second test element group die region in the first exposure and a pattern transferred from the first test element group die region in the second exposure.
6. The method of claim 5 , wherein a dicing line is not formed though the first and second test element group die regions, and individual semiconductor dice are obtained from the semiconductor wafer by dicing at regular intervals.