Granted Patent B2

US 7,605,617 · App. 11/808,575 · Granted Oct 20, 2009

Abstract

Claims (26)

1. A method for switching a system clock from a first clock signal to a second clock signal, the switching process is triggered by a select control signal and the switching occurs synchronously to the first and/or second clock signal, the method comprising:

transferring the clock control from a first predefined edge of the first clock signal to a corresponding first edge of the second clock signal;

holding, in accordance with the first clock signal, a system clock signal at a first predefined logic signal level which is the same level as a system clock hold signal, wherein a corresponding first edge of the second clock signal is awaited; and

resetting, in accordance with a received first edge of the second clock signal, the system clock hold signal to a second logic state and reactivating, via a second edge of the second clock signal, the system clock signal whereby the second clock functions as the system clock.

2. The method according to claim 1 , wherein, in accordance with the select control signal, a first clock hold signal is generated synchronously to the first clock signal by a first control module for the first clock signal, wherein the first clock hold signal is relayed to a second control module for the second clock signal, wherein a second clock hold signal is generated by the second control module synchronously to the second clock signal, wherein the system clock hold signal is generated from the first and second clock signals, wherein the second clock hold signal is relayed to the first control module, and wherein a state of the first clock hold signal is changed depending on the relayed second clock hold signal.

3. The method according to claim 1 , wherein a time since the application of the select control signal is determined and wherein the switching of the system clock signal is released when a predefined time threshold is reached.

4. The method according to claim 3 , wherein the time threshold is at least 2·T p +T s , where T p designates a cycle duration of the first clock signal and T s a cycle duration of the second clock signal.

5. The method according to claim 1 , wherein the first and second clock signals are each selected from a plurality of clock signals.

6. A clock synchronization unit for an electronic system, particularly for a microprocessor, the clock synchronization unit comprising:

a first input for a first clock signal;

a second input for a second clock signal;

a third input for a select control signal;

an output for a system clock signal;

a first control module controlled by the first clock signal; and

a second control module controlled by the second clock signal and being operatively connected to the first control module,

wherein the first control module, upon application of a predefined signal level of the select control signal at a third input synchronously with the first clock signal, is designed to set the system clock signal from the first clock signal to a predefined logic signal level as a system clock hold signal, and

wherein the second control module is designed, synchronously with the second clock signal, to reset the system clock hold signal and to cause an output of the second clock signal as the system clock signal.

7. The clock synchronization unit according to claim 6 , wherein the first control module is designed in accordance with the select control signal to generate a first clock hold signal and to relay the same to the second control module, wherein the second control module is designed upon receipt of the first clock hold signal to generate a second clock hold signal and to relay the same to the first control module, wherein the first control module is designed to reset the first clock hold signal upon receipt of the second clock hold signal, and wherein the second control module is designed to reset the second clock hold signal.

8. The clock synchronization unit according to claim 7 , further comprising a switching element, which is designed to generate the system clock hold signal from at least the first and second clock hold signals.

9. The clock synchronization unit according to claim 6 , wherein at least the first control module has a counter, which is designed to determine a time depending on the select control signal.

10. The clock synchronization unit according to claim 6 , wherein at least the first control module is designed to generate a clock switching block signal depending on the select control signal, which is applied at the second control module to prevent a resetting of the system clock hold signal.

11. The clock synchronization unit according to claim 10 , wherein the first control module is designed to turn off the clock switching block signal when a predefined time threshold is reached.

12. The clock synchronization unit according to claim 11 , wherein the time threshold is predefined by a user and/or by software, wherein the time threshold is at least 2·T p +T s , where T p designates a cycle duration of the first clock signal and T s a cycle duration of the second clock signal.

13. The clock synchronization unit according to claim 6 , further comprising a multiplexer that are each functionally connected to the first and second inputs, which are designed to select the first and second clock signal, each from a plurality of clock signals.

14. A processor unit, particularly a microprocessor, with a clock synchronization unit according to claim 6 .

15. Use of the method according to claim 1 for switching of the system clock in a processor unit or a microprocessor.

Assignments (11)