IP Library › Granted Patent US 7,733,262
Granted Patent B2
US 7,733,262 · App. 11/818,995 · Granted Jun 8, 2010

Quantizing circuits with variable reference signals

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,733,262
App. No.
11/818,995
Granted
Jun 8, 2010
Kind
B2
Abstract

Systems, methods, and devices are disclosed, such as an integrated semiconductor device that may include a data location coupled to an electrical conductor, a delta-sigma modulator coupled to the electrical conductor, a counter coupled to an output of the delta-sigma modulator, and an interfuser coupled to an output of the counter. In some embodiments, the interfuser is configured to receive two or more counts from the counter and read data conveyed by the data location based on the two or more counts.

Claims (29)

1. A device, comprising:

a data location;

an analog-to-digital converter coupled to the data location;

a counter coupled to an output of the analog-to-digital converter; and

an interfuser coupled to the counter, wherein the interfuser is configured to receive two or more counts from the counter and read data conveyed by the data location based on the two or more counts.

2. The device of claim 1 , wherein the data location comprises a floating gate transistor, a phase change memory element, or a photo diode.

3. The device of claim 1 , wherein the analog-to-digital converter comprises a delta-sigma modulator.

4. The device of claim 1 , wherein the interfuser is configured to read the data conveyed by the data location based on a product of one of the two or more counts and a weighting constant.

5. The device of claim 1 , wherein the interfuser is configured to read the data conveyed by the data location based on a slope indicated by the two or more counts.

6. The device of claim 3 , comprising a controller coupled to the delta-sigma modulator, the counter, and the interfuser.

7. The device of claim 6 , wherein the controller is configured to reset the counter after a parameter of the data location changes.

8. The device of claim 6 , wherein the controller is configured to vary a reference voltage of the delta-sigma modulator after the counter generates a first count.

9. The device of claim 8 , wherein the controller is configured to signal the interfuser when the controller varies the reference voltage of the delta-sigma modulator.

10. A system comprising:

a device comprising:

a plurality of data locations;

a quantizing circuit coupled to the plurality of data locations, wherein the quantizing circuit comprises an interfuser.

11. The system of claim 10 , wherein the quantizing circuit comprises:

an analog-to-digital converter coupled to the plurality of data locations; and

a digital filter coupled to an output of the analog-to-digital converter and an input of the interfuser.

12. The system of claim 11 , wherein the analog-to-digital converter comprises a delta-sigma modulator.

13. The system of claim 11 , wherein the digital filter comprises a counter.

14. The system of claim 10 , wherein each of the plurality of data locations comprise a floating gate transistor.

15. The system of claim 10 , wherein the interfuser comprises memory configured to store a first value from the quantizing circuit while a second value is being generated by the quantizing circuit.

16. The system of claim 10 , wherein:

the quantizing circuit is configured to sense one of the plurality of data locations using both a first reference voltage and a second reference voltage and output both a first value and a second value corresponding to the first reference voltage and the second reference voltage, respectively; and

the interfuser is configured to combine the first value with the second value to read data conveyed by the one of the plurality of data locations.

17. The system of claim 10 , wherein the plurality of data locations comprise a memory device, wherein the memory device is coupled to a processor.

18. The system of claim 17 , wherein the memory device is disposed on a memory module comprising a plurality of memory devices.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2007
From: BAKER, R. JACOB
To: MICRON TECHNOLOGY, INC.
Reel/Frame 019502/0944 →
Continuity (1)
Related Publication 20080309539A1 · Dec 18, 2008