Method of making non-volatile memory cell with embedded antifuse
View Patent ↗A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion, and forming a second electrode over the at least one nonvolatile memory cell.
1. A method of operating a nonvolatile memory device, comprising:
providing at least one nonvolatile memory cell which comprises a first diode portion, a second diode portion and an antifuse dielectric layer separating the first diode portion from the second diode portion;
applying a forward bias to the nonvolatile memory cell to rupture the antifuse dielectric layer such that a conductive link extends through the antifuse dielectric layer and such that the first diode portion and the second diode portion form a diode, and to switch the diode from the first resistivity, unprogrammed state to the second resistivity, programmed state, wherein the second resistivity state is lower than the first resistivity state;
applying a reverse bias to the diode to switch the diode to a third resistivity, unprogrammed state, wherein the third resistivity state is higher than the second resistivity state;
applying a forward bias to the diode to switch the diode to a fourth resistivity, programmed state, wherein the fourth resistivity state is lower than the third resistivity state; and
sensing a resistivity state of the diode as a data state of the memory cell.
2. The method of claim 1 , wherein:
the first diode portion comprises a p-type semiconductor region and the second diode portion comprises an n-type semiconductor region;
the antifuse comprises an antifuse dielectric layer located between the p-type semiconductor region and the n-type semiconductor region; and
an intrinsic semiconductor region is located adjacent to the antifuse dielectric layer between the p-type semiconductor region and the n-type semiconductor region.
3. A method of operating a nonvolatile memory device, comprising:
providing at least one nonvolatile memory cell which comprises a first diode portion, a second diode portion and an antifuse dielectric layer separating the first diode portion from the second diode portion, wherein a conductive link extends through the antifuse dielectric layer such that the first diode portion and the second diode portion form a diode, and the diode has been switched from the first resistivity, unprogrammed state to the second resistivity, programmed state, wherein the second resistivity state is lower than the first resistivity state;
applying a reverse bias to the diode to switch the diode to a third resistivity, unprogrammed state, wherein the third resistivity state is higher than the second resistivity state;
applying a forward bias to the diode to switch the diode to a fourth resistivity. programmed state, wherein the fourth resistivity state is lower than the third resistivity state; and
sensing a resistivity state of the diode as a data state of the memory cell.
4. The method of claim 3 , wherein:
the first diode portion comprises a p-type semiconductor region and the second diode portion comprises an n-type semiconductor region;
the antifuse comprises an antifuse dielectric layer located between the p-type semiconductor region and the n-type semiconductor region; and
an intrinsic semiconductor region is located adjacent to the antifuse dielectric layer between the p-type semiconductor region and the n-type semiconductor region.
5. A method of operating a nonvolatile memory device, comprising:
providing at least one nonvolatile memory cell which comprises a first diode portion, a second diode portion and an antifuse dielectric layer separating the first diode portion from the second diode portion, wherein a conductive link extends through the antifuse dielectric layer such that the first diode portion and the second diode portion form a diode, and the diode has been switched from the first resistivity, unprogrammed state to the second resistivity, programmed state, wherein the second resistivity state is lower than the first resistivity state; and
applying a reverse bias to the diode to switch the diode to a third resistivity, unprogrammed state, wherein the third resistivity state is higher than the second resistivity
wherein:
the diode is switched into the second, programmed state in a factory in which the memory cell is fabricated; and
the step of applying the reverse bias is performed by a user of the memory cell after the memory cell leaves the factory in which the memory cell is fabricated.
6. The method of claim 5 , wherein:
the first diode portion comprises a p-type semiconductor region and the second diode portion comprises an n-type semiconductor region;
the antifuse comprises an antifuse dielectric layer located between the p-type semiconductor region and the n-type semiconductor region; and
an intrinsic semiconductor region is located adjacent to the antifuse dielectric layer between the p-type semiconductor region and the n-type semiconductor region.