Method of making a semiconductor device with surge current protection
View Patent ↗A wide bandgap semiconductor device with surge current protection and a method of making the device are described. The device comprises a low doped n-type region formed by plasma etching through the first epitaxial layer grown on a heavily doped n-type substrate and a plurality of heavily doped p-type regions formed by plasma etching through the second epitaxial layer grown on the first epitaxial layer. Ohmic contacts are formed on p-type regions and on the backside of the n-type substrate. Schottky contacts are formed on the top surface of the n-type region. At normal operating conditions, the current in the device flows through the Schottky contacts. The device, however, is capable of withstanding extremely high current densities due to conductivity modulation caused by minority carrier injection from p-type regions.
1. A method of making a semiconductor device comprising:
selectively etching through a layer of p-type SiC semiconductor material on a layer of n-type SiC semiconductor material on an n-type SiC semiconductor substrate layer to expose the underlying n-type SiC semiconductor material in a central portion of the device; and
selectively etching through the layer of p-type semiconductor material and the layer of n-type SiC semiconductor material to expose the underlying n-type SiC semiconductor substrate layer in a peripheral portion of the device;
thereby forming a mesa structure comprising a raised region of n-type SiC semiconductor material on the n-type SiC semiconductor substrate layer having sidewalls and an upper surface and one or more discrete raised regions of p-type SiC semiconductor material on a central portion of the upper surface of the n-type SiC semiconductor material circumscribed by a continuous raised region of p-type SiC semiconductor material on a peripheral portion of the upper surface of the n-type SiC semiconductor material, wherein the continuous raised region of p-type SiC semiconductor material comprises an inner edge and an outer edge;
thermally oxidizing the semiconductor device to form an oxide layer on unetched surfaces of p-type SiC semiconductor material and on etched surfaces of the semiconductor device including the sidewalls of the raised region of n-type semiconductor material and on the exposed semiconductor substrate layer;
optionally forming one or more layers of dielectric material on the oxide layer;
selectively etching through the oxide layer and any layers of dielectric material over the discrete p-type regions and over the continuous raised region to expose the underlying p-type SiC semiconductor material;
selectively etching through the oxide layer and any layers of dielectric material over the exposed n-type SiC semiconductor material to expose the underlying n-type SiC semiconductor material in the central portion of the semiconductor device;
forming ohmic contacts on the exposed p-type SiC semiconductor material of the discrete p-type regions and on the exposed p-type SiC semiconductor material of the continuous raised region of p-type semiconductor material;
depositing Schottky metal on the ohmic contacts and on the exposed n-type SiC semiconductor material.
2. The method of claim 1 , further comprising forming a metal layer on the Schottky metal.
3. The method of claim 1 , further comprising depositing an ohmic contact on the semiconductor substrate layer opposite the layer of n-type semiconductor material.
4. The method of claim 3 , further comprising forming a metal layer on the ohmic contact on the semiconductor substrate layer.
5. The method of claim 1 , wherein the n-type SiC substrate layer has a doping concentration of >1×10 18 cm −3 .
6. The method of claim 1 , wherein the n-type SiC semiconductor layer has a doping concentration of 5×10 14 -1×10 17 cm −3 .
7. The method of claim 1 , wherein the one or more discrete raised regions of p-type SiC semiconductor material and the continuous raised region of p-type SiC semiconductor material each have a doping concentration of 5×10 14 -1×10 17 cm −3 .
8. The method of claim 1 , wherein the n-type SiC semiconductor layer has a thickness of 0.75 μm-100 μm.
9. The method of claim 1 , wherein the one or more discrete raised regions of p-type SiC semiconductor material and the continuous raised region of p-type SiC semiconductor material each have a thickness of 0.2-5 μm.
10. The method of claim 1 , wherein the ohmic contact comprises nickel.
11. The method of claim 1 , wherein the p-type SiC semiconductor material is doped with aluminum.
12. The method of claim 1 , wherein the n-type SiC semiconductor material is doped with nitrogen.
13. The method of claim 1 , wherein the continuous raised region of p-type SiC semiconductor material on the peripheral portion of the upper surface of the n-type SiC semiconductor material is a ring.
14. The method of claim 13 , wherein the ring is rectangular or square.
15. The method of claim 1 , wherein the outer edge of the continuous raised region of p-type SiC semiconductor material aligns with the sidewalls of the mesa structure.
16. The method of claim 1 , wherein the inner edge of the continuous raised region of p-type SiC semiconductor material is spaced from the one or more discrete raised regions of p-type SiC semiconductor material on the central portion of the upper surface of the n-type SiC semiconductor material.