Semiconductor memory device with on-die termination circuit

1. A semiconductor memory device, comprising:

a control signal generator for generating an initializing signal and driving clocks in response to a plurality of control signals;

a resistance control unit, initialized by the initializing signal, for generating a termination-off signal in response to the driving clocks; and

a resistance supply unit for supplying termination resistance in response to the termination-off signal and a mode register setting value,

wherein the plurality of control signals are inputted through input pins not connected to the resistance supply unit.

2. The semiconductor memory device of claim 1 , wherein the plurality of control signals used for a boundary scan test include:

a boundary-test entry signal enabled at the beginning of the boundary scan test; and

a boundary-test output control signal for controlling the output of results of the boundary scan test.

3. The semiconductor memory device of claim 2 , wherein the resistance control unit outputs the termination-off signal disabled in response to the initializing signal and enabled when the driving clocks are enabled over a predetermined number of times.

4. The semiconductor memory device of claim 3 , wherein the control signal generator includes:

a signal combination unit for generating a combination signal in response to a first and a second control signals;

an initializing signal generator for generating the initializing signal in response to the combination signal and a power-up signal; and

a driving clock generator for generating the driving clocks in response to the combination signal and a third control signal.

5. The semiconductor memory device of claim 4 , wherein the combination signal generator includes:

a first inverter for inverting the first control signal;

a second inverter for inverting the second control signal;

a first logic gate for performing a NAND operation on outputs of the first and the second inverters; and

a first inverter chain for delaying an output of the first logic gate, thereby outputting the combination signal.

6. The semiconductor memory device of claim 5 , wherein the initializing signal generator includes:

a second inverter chain for delaying the combination signal;

a third inverter for inverting the power-up signal;

a second logic gate for performing a NOR operation on outputs of the second inverter chain and the third inverter; and

a third inverter chain for delaying an output of the second logic gate, thereby outputting the initializing signal.

7. The semiconductor memory device of claim 6 , wherein the driving clock generator includes:

a fourth inverter for inverting the combination signal;

a fourth inverter chain for delaying the third control signal;

a third logic gate for performing a NAND operation on outputs of the fourth inverter and the fourth inverter chain;

a fifth inverter for generating an inverted driving clock by inverting an output of the third logic gate; and

a sixth inverter for generating a non-inverted driving clock by inverting an output of the fifth inverter.

8. The semiconductor memory device of claim 3 , wherein the resistance control unit includes first to fifth flip-flops connected in series which are initialized by the initializing signal or the power-up signal inputted through their set signal pins and latch an output of their previous flip-flop in response to the driving clocks,

wherein the first flip-flop receives a ground voltage through its data pin and the fifth flip-flop outputs the termination-off signal through its output pin.

9. The semiconductor memory device of claim 8 , wherein each of the first to fifth flip-flops includes:

a first transmission gate for transmitting a signal through a data pin in response to the disablement of the driving clocks;

a first latch for storing an output of the first transmission gate when the driving clocks are enabled;

a second transmission gate for transmitting a signal stored in the first latch in response to the enablement of the driving clocks;

a second latch for storing an output of the second transmission gate when the driving clocks are disabled;

a first inverter for inverting the output of the second transmission gate and outputting the inverted signal through an output pin; and

an initialization unit for initializing output nodes of the first and the second transmission gates in response to a signal input through a set signal pin.

10. The semiconductor memory device of claim 9 , wherein the initialization unit includes:

a PMOS transistor for providing the output node of the first transmission gate with a supply voltage in response to the signal from the set signal pin;

a second inverter for inverting the signal from the set signal pin; and

a NMOS transistor for providing the output node of the second transmission gate with the ground voltage in response to an output of the second inverter.