IP Library Granted Patent US 7,816,208
Granted Patent B2
US 7,816,208 · App. 11/822,458 · Granted Oct 19, 2010

Method of manufacturing semiconductor device having trench-gate transistor

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Quick Facts
Patent No.
US 7,816,208
App. No.
11/822,458
Granted
Oct 19, 2010
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes: a first step of forming an STI region and an active region surrounded by the STI region on a semiconductor substrate; a second step of forming a protection film protecting a shoulder part of the STI region in a boundary between the active region and the STI region; a third step of forming a gate trench in the active region so as to leave a part of the semiconductor substrate located between a side surface of the STI region and a side surface of the gate trench; a fourth step of forming a gate insulating film on the side surface of the gate trench; a fifth step of forming a gate electrode, at least a part of the gate electrode being buried in the gate trench; and a sixth step of forming a source region and a drain region in regions located on both sides of the gate trench in an extension direction of the gate trench, respectively, so that the part of the semiconductor substrate functions as a channel region.

Claims (58)

1. A method of manufacturing a semiconductor device, comprising:

a first step of forming an STI (Shallow Trench Isolation) region includes a first insulating film and an active region surrounded by the STI region on a semiconductor substrate so that an upper end of the first insulating film is lapped on an upper end of the active region and so as to include a shoulder part, the shoulder part having a surface being almost perpendicular to the semiconductor substrate;

a second step of forming a second insulating film and a third insulating film in order on an entire surface including the shoulder part;

a third step of forming a fourth insulating film on the third insulating film, the fourth insulating film serving as a hard mask when a gate trench is formed;

a fourth step of performing a dry etching using the third insulating film as an etch stopper, and forming an opening in the fourth insulating film, the opening corresponding to a width of the gate trench;

a fifth step of sequentially removing the third insulating film and the second insulating film exposed to a bottom of the opening; and

a sixth step of forming the gate trench in the semiconductor substrate using the fourth insulating film as a part of a mask and the shoulder part of the STI region as another part of the mask, the shoulder part extending in an extension direction of the gate trench, and leaving a thin film part that is a part of the semiconductor substrate between the gate trench and the STI region.

2. The method of manufacturing the semiconductor device as claimed in claim 1 , wherein

the thin film part of the semiconductor substrate includes a surface almost perpendicular to the semiconductor substrate on a side of the gate trench.

3. The method of manufacturing the semiconductor device as claimed in claim 1 , wherein

the first insulating film and the third insulating film are silicon oxide films, and the second insulating film and the fourth insulating film are silicon nitride films.

4. The method of manufacturing the semiconductor device as claimed in claim 1 , wherein

the forming the gate trench is performed using an etching, which has a high selectivity with respect to both the fourth insulating film and the first insulating film.

5. The method of manufacturing the semiconductor device as claimed in claim 1 , further comprising:

a seventh step of forming a thick insulating film on a bottom of the gate trench; and

an eighth step of forming a gate insulating film on a side surface of the gate trench, wherein

the seventh step and the eighth step are performed after the sixth step, and the thick insulating film is thicker than the gate insulating film.

6. The method of manufacturing the semiconductor device as claimed in claim 2 , further comprising:

a seventh step of forming a thick insulating film on a bottom of the gate trench; and

an eighth step of forming a gate insulating film on a side surface of the gate trench, wherein

the seventh step and the eighth step are performed after the sixth step, and the thick insulating film is thicker than the gate insulating film.

7. The method of manufacturing the semiconductor device as claimed in claim 3 , further comprising:

a seventh step of forming a thick insulating film on a bottom of the gate trench; and

an eighth step of forming a gate insulating film on a side surface of the gate trench, wherein

the seventh step and the eighth step are performed after the sixth step, and the thick insulating film is thicker than the gate insulating film.

8. The method of manufacturing the semiconductor device as claimed in claim 4 , further comprising:

a seventh step of forming a thick insulating film on a bottom of the gate trench; and

an eighth step of forming a gate insulating film on a side surface of the gate trench, wherein

the seventh step and the eighth step are performed after the sixth step, and the thick insulating film is thicker than the gate insulating film.

9. The method of manufacturing the semiconductor device as claimed in claim 5 , wherein

the seventh step includes

a step of depositing an insulating film at least on the side surface and the bottom of the gate trench by HDP (High Density Plasma)-CVD; and

a step of removing the insulating film formed on the side surface of the gate trench by wet etching.

10. The method of manufacturing the semiconductor device as claimed in claim 5 , wherein

a region under the thick insulating film on the bottom of the gate trench does not serve as a channel region.

11. The method of manufacturing the semiconductor device as claimed in claim 6 , wherein

a region under the thick insulating film on the bottom of the gate trench does not serve as a channel region.

12. The method of manufacturing the semiconductor device as claimed in claim 7 , wherein

a region under the thick insulating film on the bottom of the gate trench does not serve as a channel region.

13. The method of manufacturing the semiconductor device as claimed in claim 8 , wherein

a region under the thick insulating film on the bottom of the gate trench does not serve as a channel region.

14. A method of manufacturing a semiconductor device, comprising:

a first step of forming an STI (Shallow Trench Isolation) region and an active region surrounded by the STI region on a semiconductor substrate;

a second step of forming a protection film protecting a shoulder part of the STI region in a boundary between the active region and the STI region;

a third step of forming a gate trench, using the shoulder part as a mask, in the active region so as to leave a part of the semiconductor substrate located between a side surface of the STI region and a side surface of the gate trench;

a fourth step of forming a gate insulating film on the side surface of the gate trench;

a fifth step of forming a gate electrode, at least a part of the gate electrode being buried in the gate trench; and

a sixth step of forming a source region and a drain region in regions located on both sides of the gate trench in an extension direction of the gate trench, respectively, so that the part of the semiconductor substrate functions as a channel region.

15. The method of manufacturing the semiconductor device as claimed in claim 14 , wherein

a part of the protection film is removed after the second step and before the third step, the part of the protection film being where the gate trench is formed in the third step.

16. The method of manufacturing the semiconductor device as claimed in claim 14 , wherein

the protection film includes a plurality of insulating films different in material.

17. The method of manufacturing the semiconductor device as claimed in claim 15 , wherein

the protection film includes a plurality of insulating films different in material.

18. The method of manufacturing the semiconductor device as claimed in claim 16 , wherein

at least one insulating film of the plurality of insulating films included in the protection film is made of a material different from a material of a mask used at the third step.

19. The method of manufacturing the semiconductor device as claimed in claim 17 , wherein

at least one insulating film of the plurality of insulating films included in the protection film is made of a material different from a material of a mask used at the third step.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 6, 2007
From: KUJIRAI, HIROSHI
To: ELPIDA MEMORY, INC.
Reel/Frame 019576/0038 →