High density NOR flash array architecture
View Patent ↗In one embodiment of the invention, a memory includes wordline jogs and adjacent spacers. Spacers from different wordlines may contact one another on either side of a drain contact and consequently isolate and self-align the contact in the horizontal and vertical directions.
1. A NOR flash memory array comprising:
a first pair of parallel address lines;
a second pair of parallel address lines generally perpendicular to said first pair of address lines;
a first pair of spacers extending along said first pair of address lines; and
a contact to one of said second pair of address lines, said contact being completely surrounded by said first pair of spacers.
2. The array of claim 1 including:
a first bitline and a second bitline;
a first source line and a second source line;
a first wordline coupled to a first spacer and a second spacer;
a second wordline coupled to a third spacer and a fourth spacer;
a first drain contact coupled to the first bitline and a second drain contact coupled to the second bitline;
a first source contact coupled to the first source line and a second source contact coupled to the second source line;
wherein the second spacer couples to the third spacer and the second spacer and the third spacer collectively surround the first drain contact in a first plane.
3. The NOR flash array of claim 2 , wherein the second spacer directly connects to the third spacer in a first location and a second location and the first drain contact directly connects to the first location and the second location.
4. The NOR flash array of claim 2 , wherein the first drain contact directly connects to a rounded portion of the second spacer and to a rounded portion of the third spacer.
5. The NOR flash array of claim 2 , wherein the first bit line includes a horizontal diameter and the first drain contact includes a horizontal diameter and a vertical diameter; the first bit line horizontal diameter being less than 60 nm, the first drain contact horizontal diameter being at least 110 nm and the first drain contact vertical diameter being at least 50 nm.
6. The NOR flash array of claim 2 , wherein the first drain contact is operatively coupled to four memory cells.
7. The NOR flash array of claim 2 , wherein the first source contact is to couple to a virtual ground formed in the NOR flash array.
8. The NOR flash array of claim 2 , further comprising:
a third wordline coupled to a fifth spacer and a sixth spacer;
wherein the fourth spacer couples to the fifth spacer and the fourth spacer and the fifth spacer collectively surround the first source contact in the first plane.
9. The NOR flash array of claim 2 , wherein the first drain contact is self-aligned in a vertical dimension and a horizontal dimension of the first plane.
10. A method comprising:
forming a first pair of parallel address lines;
forming a second pair of parallel address lines generally perpendicular to said first pair of address lines;
forming a first pair of spacers extending along said first pair of address lines;
forming a contact to one of said second pair of address lines; and
completely surrounding said contact by said first pair of spacers.
11. The method of claim 10 including:
forming a first bitline and a second bitline in a memory array;
forming a first source line and a second source line;
forming a first wordline coupled to a first spacer and a second spacer;
forming a second wordline coupled to a third spacer and a fourth spacer;
coupling a first transistor node contact to the first bitline and a second transistor node contact to the second bitline;
coupling the second spacer to the third spacer; and
isolating the first transistor node contact in a first plane using the second spacer and the third spacer.
12. The method of claim 11 , further comprising forming the second spacer to directly connect to the third spacer in a first location and a second location.
13. The method of claim 11 , further comprising directly connecting a rounded portion of the second spacer and a rounded portion of the third spacer to the first transistor node contact.
14. The method of claim 11 , further comprising forming the first transistor node contact to operatively couple to four memory cells.
15. The method of claim 11 , further comprising selecting a first memory cell by selecting the first wordline, the first bitline, and the first source line.
16. The method of claim 11 , further comprising isolating the second transistor node contact in the first plane using the second spacer and the third spacer.
17. The method of claim 11 , further comprising forming the second spacer and the third spacer to self-align the first transistor node contact in a vertical dimension and a horizontal dimension of the first plane.