Internal voltage generating circuit

1. An internal voltage generating circuit comprising: a first detector configured to compare an internal voltage and a first reference voltage and to output a first detection signal based on the comparison;

a second detector configured to compare a supply voltage and a second reference voltage and to output a second detection signal based on the comparison;

a loop selection oscillator configured to perform an oscillation operation in response to the first detection signal, select a first loop or a second loop for performing the oscillation operation in response to the second detection signal to obtain the selected loop, and output an oscillation signal from the selected loop; and

a charge pump configured to perform a pumping operation according to the oscillation signal output from the loop selection oscillator and generate the internal voltage.

2. The internal voltage generating circuit of claim 1 ,

wherein the loop selection oscillator has an oscillation period that is shorter when the loop selection oscillator selects the first loop compared to when the loop selection oscillator selects the second loop.

3. The internal voltage generating circuit of claim 2 ,

wherein the loop selection oscillator is configured to select the second loop when the second detection signal indicates that the supply voltage is higher than the second reference voltage, and to select the first loop when the second detection signal indicates that the supply voltage is lower than the second reference voltage.

4. The internal voltage generating circuit of claim 3 ,

wherein the loop selection oscillator includes:

a first loop logic gate unit including logic gates configured to receive the first detection signal and that form part of both the first loop and the second loop and to provide an output;

a second loop logic gate unit including logic gates that form part of the second loop and not part of the first loop and that provide an output; and

a selection logic gate unit configured to receive the second detection signal, select either the first loop or the second loop to be selectively operated in accordance with the second detection signal and outputs a signal based thereon.

5. The internal voltage generating circuit of claim 4 ,

wherein the loop selection oscillator further includes a driving unit coupled to the selection logic gate unit and configured to also select the first loop or the second loop in accordance with a control signal.

6. The internal voltage generating circuit of claim 4 ,

wherein the logic gates of the first loop logic gate unit include a chain of logic gates configured to invert the signal output from the selection logic gate unit in accordance with the first detection signal.

7. The internal voltage generating circuit of claim 6 ,

wherein the chain of logic gates of the first loop logic gate unit includes:

a first inverter configured to receive the signal output from the selection logic gate unit as an input and to provide an output;

a NOR gate configured to receive the first detection signal and the output of the first inverter as inputs and to provide an output; and

a second inverter configured to receive the output of the NOR gate as an input and having an output coupled to an input of the selection logic gate unit.

8. The internal voltage generating circuit of claim 4 ,

wherein the logic gates of the second loop logic gate unit include a chain of logic gates configured to receive the output of the first loop logic gate unit as an input.

9. The internal voltage generating circuit of claim 8 ,

wherein the chain of logic gates in the second loop logic gate unit includes a chain of inverters configured to invert the output of the first loop logic gate unit and having an output coupled to an input of the selection logic gate unit.

10. The internal voltage generating circuit of claim 4 ,

wherein the selection logic gate unit includes logic gates configured to drive the first loop or the second loop in accordance with the second detection signal.

11. The internal voltage generating circuit of claim 10 ,

wherein the logic gates of the selection logic gate unit include:

a first NAND gate configured to receive the output of the first loop logic gate unit and the second detection signal as inputs and to provide an output based thereon;

a second NAND gate configured to receive the output of the second loop logic gate unit and an inverted signal of the second detection signal as inputs and to provide an output based thereon; and

a third NAND gate configured to receive the outputs of the first NAND gate and the second NAND gate and output an operation result to the first loop logic gate unit.

12. An internal voltage generating circuit comprising:

a multiple detector configured to compare an internal voltage and a first reference voltage to output a first detection signal, and compare a supply voltage and a second reference voltage to output a second detection signal;

a loop selection oscillator configured to perform an oscillation operation in response to the first detection signal, select a first loop or a second loop to obtain the selected loop for performing the oscillation operation in response to the second detection signal, and to output an oscillation signal from the selected loop; and

a charge pump configured to perform a pumping operation according to the oscillation signal output from the loop selection oscillator and generate the internal voltage.

13. The internal voltage generating circuit of claim 12 , wherein the loop selection oscillator is configured to select the second loop when the second detection signal indicates that the supply voltage is higher than the second reference voltage, and to select the first loop when the second detection signal indicates that the supply voltage is lower than the second reference voltage.

14. The internal voltage generating circuit of claim 13 ,

wherein the loop selection oscillator includes:

a first loop logic gate unit including logic gates configured to receive the first detection signal as an input and that form part of both the first loop and the second loop;

a second loop logic gate unit including logic gates that are part of the second loop and not part of the first loop; and

a selection logic gate unit configured to receive the second detection signal, and select either the first loop or the second loop to be selectively operated in accordance with the output of the second detection signal.

15. The internal voltage generating circuit of claim 14 ,

wherein the loop selection oscillator further includes a driving unit coupled to the selection logic gate unit and configured to also select the first loop or the second loop in accordance with a control signal.

16. The internal voltage generating circuit of claim 15 ,

wherein the logic gates of the first loop logic gate unit include:

a first inverter configured to receive an output of the selection logic gate unit as an input and to provide an output based thereon;

a NOR gate configured to receive the first detection signal and the output of the first inverter and to provide an output based thereon; and

a second inverter configured to receive the output of the NOR gate as an input and to provide an output to the selection logic gate unit.

17. The internal voltage generating circuit of claim 16 ,

wherein the logic gates of the second loop logic gate unit include a chain of inverters configured to invert an output of the first loop logic gate unit and having an output coupled to an input of the selection logic gate unit.

18. The internal voltage generating circuit of claim 17 ,

wherein the selection logic gate unit includes:

a first NAND gate configured to receive the output of the first loop logic gate unit and the second detection signal as inputs and to provide an output based thereon;

a second NAND gate configured to receive the output of the second loop logic gate unit and an inversion signal of the second detection signal as inputs and to provide an output based thereon; and

a third NAND gate configured to receive the outputs of the first NAND gate and the second NAND gate and output an operation result to the first loop logic gate unit.