Semiconductor memory device and fabrication method thereof
View Patent ↗A semiconductor memory device comprises a heater electrode, a phase change portion, and an upper electrode. The phase change portion is connected to the heater electrode in a first direction. The upper electrode has an upper surface, a lower surface and a hole. The hole pierces the upper electrode between the upper and the lower surfaces in the first direction. The hole has an inner wall, which is connected to the phase change portion in a second direction perpendicular to the first direction.
1. A semiconductor memory device comprising:
a heater electrode extending in a first direction;
a phase change portion directly connected to an end of the heater electrode extending in the first direction; and
an upper electrode having an upper surface, a lower surface and a hole, the hole piercing the upper electrode between the upper and the lower surfaces in the first direction, the hole having an inner wall, the inner wall being connected to the phase change portion in a second direction perpendicular to the first direction.
2. The semiconductor memory device according to claim 1 , wherein the upper electrode completely surrounds and is connected to the phase change portion in a plane perpendicular to the first direction.
3. The semiconductor memory device according to claim 1 , wherein an area of the hole covers a top surface of the heater electrode in plan view.
4. The semiconductor memory device according to claim 1 , wherein the phase change portion extends across the lower surface of the upper electrode in the first direction and reaches the upper surface of the upper electrode.
5. The semiconductor memory device according to claim 4 , wherein the phase change portion extends further across the upper surface of the upper electrode in the first direction.
6. The semiconductor memory device according to claim 1 , wherein the phase change portion has a top surface, a bottom surface and a side surface, the bottom surface being connected to the heater electrode, the side surface connecting between the top and the bottom surface and being connected to the upper electrode.
7. The semiconductor memory device according to claim 6 , wherein the upper electrode is connected to the phase change portion only on the side surface thereof.
8. The semiconductor memory device according to claim 6 , wherein the top surface of the phase change portion has a closed loop-like shape and has an inner edge, the phase change portion further comprising a concave portion, the concave portion being depressed downwardly from the inner edge of the top surface.
9. The semiconductor memory device according to claim 8 , further comprising a heat insulation portion formed of a heat insulation material in the concave portion.
10. The semiconductor memory device according to claim 9 , wherein the heat insulation portion comprises two or more heat insulation layers.
11. The semiconductor memory device according to claim 1 , wherein the heater electrode comprises two or more heater pillars, at least two of the heater pillars being connected to the phase change portion.
12. A semiconductor memory device comprising:
a heater electrode;
two or more phase change portions connected to the heater electrode in a first direction; and
an upper electrode having an upper surface, a lower surface and a hole, the hole piercing the upper electrode between the upper and the lower surfaces in the first direction, the hole having an inner wall, the inner wall being connected to the phase change portion in a second direction perpendicular to the first direction,
wherein the upper electrode extends in the second direction and is formed with two or more of the piercing holes, the phase change portions being formed in and being connected to the piercing holes, respectively.
13. A semiconductor memory device comprising:
a heater electrode extending in a first direction;
a phase change portion directly connected to an end of the heater electrode extending in the first direction; and
an upper electrode having an upper surface, a lower surface and a hole, the hole penetrating the upper electrode between the upper and the lower surfaces in the first direction, the upper electrode including an outer wall that defines a peripheral edge thereof and an inner wall that is defined by the hole,
wherein the inner wall is disconnected from the outer wall, and the inner wall is connected directly to the phase change portion in a second direction perpendicular to the first direction.
14. The semiconductor memory device of claim 13 , wherein the phase change portion is free from contact with the outer wall of the upper electrode.