Semiconductor memory device
Disclosed is a semiconductor memory device capable of realizing reduction in an SRAM unit cell area. Using as a standard configuration a parallel-type SRAM unit cell having each pair of load transistors, driver transistors and transfer transistors, all or a part of the gate electrodes and active regions configuring at least any one of the pairs of the transistors, for example, the pair of the transfer transistors are configured obliquely in a predetermined direction from the standard configuration. As a result, a size in a cell outside part including the driver transistor and the transfer transistor is reduced. At the same time, a distance between the load transistors in the central part is reduced as compared with that in the standard configuration. Thus, area reduction in the whole SRAM unit cell is realized.
1. A semiconductor memory device, comprising:
a first p-type active region;
a second p-type active region formed in a first direction a first distance away from the first p-type active region;
a first n-type active region formed a second distance away from the first p-type active region between the first p-type active region and the second p-type active region;
a second n-type active region formed a third distance away from the first p-type active region between the first p-type active region and the second p-type active region, the third distance being longer than the second distance;
a first n-type transistor having a first gate electrode formed on the first p-type active region;
a third n-type transistor having a third gate electrode formed on the first p-type active region;
a second n-type transistor having a second gate electrode formed on the second p-type active region;
a fourth n-type transistor having a fourth gate electrode formed on the second p-type active region;
a first p-type transistor having a fifth gate electrode formed on the first n-type active region;
a second p-type transistor having a sixth gate electrode formed on the second n-type active region;
a first contact connected to the fifth gate electrode of the first p-type transistor;
a second contact connected to a second drain electrode of the second p-type transistor;
a third contact connected to the sixth gate electrode of the second p-type transistor;
a fourth contact connected to the first drain electrode of the first p-type transistor;
a fifth contact connected to a third drain electrode of the first n-type transistor; and
a sixth contact connected to a fourth drain electrode of the second n-type transistor;
wherein:
the first contact, the second contact and the sixth contact are electrically connected to each other,
the third contact, the fourth contact and the fifth contact are electrically connected to each other,
the third gate electrode and the fifth gate electrode are electrically connected to each other,
the fourth gate electrode and the sixth gate electrode are electrically connected to each other,
the first contact is arranged between the second p-type active region and the first n-type active region,
the third contact is arranged between the first p-type active region and the second n-type active region,
the first gate electrode is arranged in a second direction perpendicular to the first direction with respect to the third gate electrode, and
the fourth gate electrode is arranged in the second direction with respect to the second gate electrode, and
wherein:
the fifth gate electrode and the sixth gate electrode extend in the first direction, and a pair of the first gate electrode and the second gate electrode, a pair of the third gate electrode and the fourth gate electrode, or a combination thereof is configured to extend obliquely with respect to the first direction, or
the first gate electrode and the second gate electrode extend in the first direction, and a pair of the third gate electrode and the fourth gate electrode, a pair of the fifth gate electrode and the sixth gate electrode, or a combination thereof is configured to extend obliquely with respect to the first direction, or
the third gate electrode and the fourth gate electrode extend in the first direction, and a pair of the first gate electrode and the second gate electrode, a pair of the fifth gate electrode and the sixth gate electrode, or a combination thereof is configured to extend obliquely with respect to the first direction.
2. The semiconductor memory device according to claim 1 , wherein the pair of the first gate electrode and the second gate electrode, the pair of third gate electrode and the fourth gate electrode, or the pair of the fifth gate electrode and the sixth gate electrode are configured to extend obliquely in a same rotation direction with respect to the first direction.
3. The semiconductor memory device according to claim 1 , wherein the pair of the first gate electrode and the second gate electrode, the pair of the third gate electrode and the fourth gate electrode, or the pair of the fifth gate electrode and the sixth gate electrode are configured to extend obliquely at 45° or less with respect to the first direction.
4. The semiconductor memory device according to claim 1 , wherein, in a case where the first and second gate electrodes extend in the first direction and the fifth and sixth gate electrodes extend obliquely with respect to the first direction, ends of the first and second gate electrodes are configured obliquely in a direction apart from the first and second p-type transistors, respectively.
5. The semiconductor memory device according to claim 1 , wherein:
each of the first and second p-type transistors has a source electrically connected to a power supply line;
each of the third and fourth n-type transistors has a source electrically connected to a grounding line;
the first and second n-type transistors have sources electrically connected to a first and second bit lines, respectively; and
the first and second gate electrodes are electrically connected to a common word line.