CMOS logic compatible non-volatile memory cell structure, operation, and array configuration
View Patent ↗The present invention is to provide a logic based single-poly non-volatile memory cell which is compatible with the CMOS process, uses lower voltages for operating, and is more reliable in program, read, or erase operation. A non-volatile memory cell in accordance with the present invention comprises a program transistor with a program transistor source as a first program terminal; a select transistor with a select transistor gate as a select terminal and a select transistor drain as a second program terminal; and an erase transistor with an erase transistor source and an erase transistor drain connected as an erase terminal, wherein the erase transistor shares a floating gate with the program transistor and the drain program transistor is connected to the select transistor source. By employing the present invention, significant cost advantages in feature-rich semiconductor products, such as System-on-Chip (SoC) design, compared to conventional dual-poly floating gate embedded Flash memory are provided.
1. A non-volatile memory cell comprising:
a program transistor with its source as a first program terminal;
a select transistor with its gate as a select terminal and a drain as a second program terminal; and
an erase transistor with its source and drain connected as an erase terminal,
wherein the erase transistor shares a floating gate with the program transistor and the drain of the program transistor is connected to the source of select transistor; and
wherein the cell is programmed by applying a first voltage on the first program terminal, floating the select terminal, and grounding the second program terminal.
2. The non-volatile memory cell as claimed in claim 1 , wherein the program transistor and the select transistor reside in a same WELL.
3. The non-volatile memory cell as claimed in claim 1 , wherein the program transistor and the select transistor reside in a same NWELL, while the erase transistor resides in a separate NWELL.
4. The non-volatile memory cell as claimed in claim 1 , wherein the program transistor and the select transistor are PMOS transistors.
5. The non-volatile memory cell as claimed in claim 1 , wherein the erase transistor is a NMOSFET residing in a P-substrate.
6. The non-volatile memory cell as claimed in claim 3 , wherein the erase transistor is a P doped PMOSFET.
7. The non-volatile memory cell as claimed in claim 3 , wherein a MOS capacitor comprising an N doped region is used in place of the erase transistor.
8. The non-volatile memory cell as claimed in claim 1 , wherein the erase transistor is much smaller than the program transistor.
9. A non-volatile storage device, comprising:
a plurality of cells, each cell comprising:
a program transistor with its source as a first program terminal;
a select transistor with its gate as a select terminal and a drain as a second program terminal; and
an erase transistor with its source and drain connected as an erase terminal,
wherein the erase transistor shares a floating gate with the program transistor and the drain of the program transistor is connected to the source of select transistor, wherein the plurality of cells are arranged such that the second program terminals of cells in a column are connected as a bit line, while the first program terminals of cells in a row are connected as a word line, the select terminals thereof are connected as a select line, and the erase terminals thereof are connected as an erase line, and
the device further comprising a program mechanism, wherein the program mechanism functions by applying a first voltage on the word line, floating the select line, and grounding the bit line.
10. The non-volatile storage device as claimed in claim 9 , wherein the program transistor and the select transistor reside in a same WELL.
11. The non-volatile storage device as claimed in claim 9 , wherein the program transistor and the select transistor reside in a same NWELL, while the erase transistor resides in a separate NWELL.
12. The non-volatile storage device as claimed in claim 9 , wherein the program transistor and the select transistor are PMOS transistors.
13. The non-volatile storage device as claimed in claim 10 , wherein the erase transistor is a NMOSFET and resides in a P-substrate.
14. The non-volatile storage device as claimed in claim 11 , wherein the erase transistor is a P doped PMOSFET.
15. The non-volatile storage device as claimed in claim 11 , wherein a MOS capacitor comprising an N doped region is used in place of the erase transistor.
16. The non-volatile storage device as claimed in claim 9 , wherein the erase transistor is much smaller than the program transistor.
17. The non-volatile storage device as claimed in claim 9 , further comprising a program mechanism, wherein the program mechanism functions by applying a first voltage on the word line and grounding the select line and the bit line, wherein the first voltage is substantially not higher than 5V.
18. The non-volatile storage device as claimed in claim 9 , wherein the first voltage is substantially not higher than 7V.
19. The non-volatile storage device as claimed in claim 17 , further comprising a program inhibit mechanism, wherein the program inhibit mechanism functions by floating the bit line or grounding the word line.
20. The non-volatile storage device as claimed in claim 18 , further comprising a program inhibit mechanism, wherein the program inhibit mechanism functions by floating the erase line.
21. The non-volatile storage device as claimed in claim 9 , further comprising an erase mechanism, wherein the erase mechanism functions by applying a second voltage on the erase line, wherein the second voltage is substantially not higher than 7V.
22. The non-volatile storage device as claimed in claim 9 , further comprising a read mechanism, wherein the read mechanism functions by applying a third voltage on the select line and a fourth voltage on the bit line, said third voltage or the fourth voltage is significantly lower than the first voltage.
23. The non-volatile storage device as claimed in claim 17 , wherein the program mechanism functions by Channel Hot Electron (CHE) Injection.
24. The non-volatile storage device as claimed in claim 18 , wherein the program mechanism functions by Fowler-Nordheim (FN) Tunneling.
25. The non-volatile storage device as claimed in claim 21 , wherein the erase mechanism functions by Fowler-Nordheim (FN) Tunneling.
26. The non-volatile storage device as claimed in claim 9 , further comprising a high-voltage charge pump and a high-voltage switch.
27. The non-volatile storage device as claimed in claim 21 , further comprising a read mechanism, wherein the read mechanism functions by applying a third voltage on the select line and a fourth voltage on the bit line, the third voltage or the fourth voltage being significantly lower than the second voltage.