Differential sensing with high common mode rejection
View Patent ↗A differential operation circuit that uses the differential input signals to generate a reference voltage that fluctuates with the common mode voltage of the differential input signals. The reference voltage includes a common mode component that generally follows the common mode voltage of the differential input signals. The common mode component of the reference voltage is used to fully or almost fully offset the common mode voltage of the differential input signals, thereby increasing the differential operation circuit's common mode rejection characteristics.
1. A differential operation circuit comprising:
a first differential input node;
a second differential input node;
a common mode following circuit configured such that, when a first differential input signal is applied to the first differential input node and a second differential input signal is applied to the second differential input node, the common mode following circuit generates at least one signal that at least partially follows a common mode of the first and second differential input signals;
a first differential output signal generation circuit configured to:
A) be coupled to the first differential input node so as to receive at least a derivative of the first differential input signal when the first differential input signal is applied to the first differential input node, wherein the at least the derivative of the first differential input signal includes a common mode component;
B) be coupled to the common mode following circuit so as to receive at least a derivative of a first signal generated by the common mode following circuit, the first signal generated by the common mode following circuit including a common mode component; and
C) generate a first differential output signal that uses the common mode component of the at least the derivative of the first differential input signal and the common mode component of the at least the derivative of the first signal generated by the common mode following circuit in a manner that reduces a common mode component of the first differential output signal; and
a second differential output signal generation circuit configured to:
A) be coupled to the second differential input node so as to receive at least a derivative of the second differential input signal when the second differential input signal is applied to the second differential input node, wherein the at least the derivative of the second differential input signal includes a common mode component;
B) be coupled to the common mode following circuit so as to receive at least a derivative of a second signal generated by the common mode following circuit, the second signal generated by the common mode following circuit including a common mode component; and
C) generate a second differential output signal that uses the common mode component of the at least the derivative of the second differential input signal and the common mode component of the at least the derivative of the second signal generated by the common mode following circuit in a manner that reduces a common mode component of the second differential output signal.
2. A differential operation circuit in accordance with claim 1 , wherein the first signal generated by the common mode following circuit, and the second signal generated by the common mode following circuit, are the same signal.
3. A differential operation circuit in accordance with claim 1 , wherein the common mode following circuit comprises:
a current source or sink that provides current to, or receives current from, an intermediate node;
a first resistor coupled between the first differential input node and the intermediate node that receives current from or provides current to the current source or sink; and
a second resistor coupled between the second differential input node and the intermediate node that receivers current from or provides current to the current source or sink.
4. A differential operation circuit in accordance with claim 3 , wherein the first and second resistors are matched.
5. A differential operation circuit in accordance with claim 3 , wherein the first and second resistors are not matched.
6. A differential operation circuit in accordance with claim 3 , wherein the common mode following circuit further comprises:
a diode coupled to be forward biased between the current source or sink and the intermediate node.
7. A differential operation circuit in accordance with claim 6 , wherein
the diode is a diode-connected nMOS transistor,
the current source or sink is a current source,
the first differential output signal generation circuit comprises a first nMOS transistor having a gate terminal connected to a drain and gate terminal of the diode-connected nMOS transistor, having a source terminal connected to the first differential input node, and having a drain terminal connected to a first differential current output node; and
the second differential output signal generation circuit comprises a second nMOS transistor having a gate terminal connected to a drain and gate terminal of the diode-connected nMOS transistor, having a source terminal connected to the second differential input node, and having a drain terminal connected to a second differential current output node.
8. A differential operation circuit in accordance with claim 7 ,
wherein the first differential output signal generation circuit further comprises a third resistor coupled between the source terminal of the first nMOS transistor, and the first differential input node; and
wherein the second differential output signal generation circuit further comprises a fourth resistor coupled between the source terminal of the second nMOS transistor and the second differential input node, wherein the third resistor and the fourth resistor are matched.
9. A differential operation circuit in accordance with claim 7 ,
wherein the first differential output signal generation circuit further comprises a third resistor coupled between the source terminal of the first nMOS transistor, and the first differential input node; and
wherein the second differential output signal generation circuit farther comprises a fourth resistor coupled between the source terminal of the second nMOS transistor and the second differential input node, wherein the third resistor and the fourth resistor are not matched.
10. A differential operation circuit in accordance with claim 7 , wherein the common mode following circuit farther comprises:
a first capacitor coupled between the drain terminal of the first nMOS transistor and the first different input node; and
a second capacitor coupled between the drain terminal of the second nMOS transistor and the second differential input node.
11. A differential operation circuit in accordance with claim 10 , further comprising:
a current to voltage conversion circuit coupled to the first and second current output nodes and configured to convert differential current signals present on the first and second current output nodes into a differential output voltage signal.
12. A differential operation circuit in accordance with claim 6 , further comprising:
a current to voltage conversion circuit coupled to the first and second current output nodes and configured to convert differential current signals present on the first and second current output nodes into a differential output voltage signal.
13. A differential operation circuit in accordance with claim 6 , wherein
the diode is a diode-connected pMOS transistor,
the current source or sink is a current sink,
the first differential output signal generation circuit comprises a first pMOS transistor having a gate terminal connected to a drain and gate terminal of the diode-connected pMOS transistor, having a source terminal connected to the first differential input node, and having a drain terminal connected to a first differential current output node; and
the second differential output signal generation circuit comprises a second pMOS transistor having a gate terminal connected to a drain and gate terminal of the diode-connected pMOS transistor, having a source terminal connected to the second differential input node, and having a drain terminal connected to a second differential current output node.
14. A differential operation circuit in accordance with claim 13 ,
wherein the first differential output signal generation circuit further comprises a third resistor coupled between the source terminal of the first pMOS transistor, and the first differential input node; and
wherein the second differential output signal generation circuit farther comprises a fourth resistor coupled between the source terminal of the second pMOS transistor and the second differential input node, wherein the third resistor and the fourth resistor are matched.
15. A differential operation circuit in accordance with claim 13 ,
wherein the first differential output signal generation circuit further comprises a third resistor coupled between the source terminal of the first pMOS transistor, and the first differential input node; and
wherein the second differential output signal generation circuit farther comprises a fourth resistor coupled between the source terminal of the second pMOS transistor and the second differential input node, wherein the third resistor and the fourth resistor are not matched.
16. A differential operation circuit in accordance with claim 13 , wherein the common mode following circuit farther comprises:
a first capacitor coupled between the drain terminal of the first pMOS transistor and the first different input node; and
a second capacitor coupled between the drain terminal of the second pMOS transistor and the second differential input node.
17. A differential operation circuit in accordance with claim 16 , further comprising:
a current to voltage conversion circuit coupled to the first and second current output nodes and configured to convert differential current signals present on the first and second current output nodes into a differential output voltage signal.
18. A differential operation circuit in accordance with claim 12 , further comprising:
a current to voltage conversion circuit coupled to the first and second current output nodes and configured to convert differential current signals present on the first and second current output nodes into a differential output voltage signal.