Method for manufacturing a semiconductor device having a polymetal gate electrode structure
View Patent ↗A process for manufacturing a semiconductor device having a polymetal structure includes patterning a bottom electrode layer by using a sacrificial layer pattern oxidizing the side surface of the patterned bottom electrode layer, forming a sidewall oxide film on both the patterned bottom electrode layer and the sacrificial layer pattern, removing the sacrificial layer pattern, and forming a top electrode layer on the exposed bottom electrode layer and the side surface of the sidewall oxide film.
1. A method for manufacturing a semiconductor device comprising in order:
consecutively depositing a bottom electrode layer and a sacrificial layer on a semiconductor substrate with an intervention of a gate insulating film;
patterning said bottom electrode layer and sacrificial layer to form bottom electrode pattern and sacrificial layer pattern;
forming a sidewall insulating film on a side surface of both said bottom electrode pattern and said sacrificial layer pattern;
forming contact plugs on said semiconductor substrate in self-alignment with said sidewall insulating film; and
heat treating said contact plugs to reduce a contact resistance between said contact plugs and said semiconductor substrate;
removing said sacrificial layer pattern to expose a top surface of said bottom electrode pattern and a side surface of said sidewall insulating film; and
forming a top electrode film on said bottom electrode film and said side surface of said sidewall insulating film.
2. The method according to claim 1 , further comprising between said patterning and said forming said sidewall insulating film:
oxidizing a side surface of said bottom electrode film.
3. The method according to claim 1 , further comprising subsequent to said forming said top electrode:
removing some of said contact plugs by using a mask.
4. The method according to claim 1 , wherein said bottom electrode layer includes polysilicon.
5. The method according to claim 4 , wherein said top electrode layer includes at least one of tungsten and titanium.
6. The method according to claim 1 , further comprising prior to said depositing:
forming a trench on said semiconductor substrate;
embedding an insulating film in said trench; and
removing a top portion of said insulating film within said trench.
7. The method according to claim 6 , wherein said depositing step comprises flattening a top surface of said bottom electrode layer.
8. The method according to claim 1 , wherein the first insulating layer is silicon nitride, and the sidewall insulating film is silicon oxide.
9. A method for manufacturing a semiconductor device comprising in order:
forming first and second structures overlying a substrate, wherein the first and second structures are apart from each other to form a gap structure, and each of the first and second structures has a first conductive layer and a first insulating layer on the first conductive layer;
forming a sidewall insulating film on each of side surfaces of the first and second structures;
filling the gap structure with a third conductive layer;
removing the first insulating layers of each of the first and second structures to expose top surfaces of the first conductive layers of each of the first and second structures; and
forming a second conductive layer on the first conductive layer of each of the first and second structures.
10. The method according to claim 9 , wherein said forming the second conductive layer comprises covering the first and third conductive layers with a conductive material layer, and performing planarization process on the conductive material layer to divide the conductive material layer into the second conductive layer on the first conductive layer of each of the first and second structures and to expose a surface of the third conductive layer.
11. The method according to claim 10 , further comprising:
forming a second insulating layer over the second and third conductive layers; and
forming a contact plug selectively in the second insulating layer in contact with the third conductive layer.
12. A method for manufacturing a semiconductor device comprising in order:
forming first and second structures over a substrate, wherein the first and second structures are apart from each other to form a gap, and each of the first and second structures has a first conductive layer and a first insulating layer on the first conductive layer;
forming a sidewall insulating film on each of side surfaces of the first and second structures;
forming a third conductive layer on the first insulating layer and the sidewall insulating film to cover the gap;
performing a planarization process on the third conductive layer to leave the third conductive layer in the gap and to expose a top surface of the first insulating layer;
removing the first insulating layers of each of the first and second structures to expose top surfaces of the first conductive layers of each of the first and second structures;
forming a second conductive layer on the first conductive layer of each of the first and second structures; and
removing a part of the third conductive layer by using a mask and an etching process to make contact plugs.
13. The method according to claim 12 , wherein forming the second conductive layer comprises covering the first and third conductive layer with a conductive material layer, and performing another planarization process on the conductive material layer to divide the conductive material layer into the second conductive layer on the first conductive layer of each of the first and second structures and to expose a surface of the third conductive layer.