PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DEPOSITING LAYERS WITHIN OPENINGS

1 . A process of forming an electronic device comprising:

depositing a first layer over a substrate, wherein depositing the first layer is performed at a first alternating current (“AC”) power; and

depositing a second layer after depositing the first layer, wherein depositing the second layer is performed at a second AC power that is different from the first AC power.

2 . The process of claim 1 , wherein the first layer and the second layer comprise a same metallic element.

3 . The process of claim 1 , further comprising depositing a third layer after depositing the second layer, wherein depositing the third layer is performed at a third AC power that is between the first AC power and the second AC power.

4 . The process of claim 3 , wherein the first layer, the second layer, and the third layer comprise substantially the same composition, and wherein the second layer lies between and contacts the first layer and the third layer.

5 . The process of claim 3 , wherein depositing the first layer, depositing the second layer, and depositing the third layer are performed using a physical vapor deposition technique.

6 . The process of claim 3 , further comprising:

forming a dielectric layer over the substrate before forming the first layer;

patterning the dielectric layer to define an opening before forming the first layer; and

forming an insulating layer along a bottom of the opening before forming the first layer.

7 . The process of claim 6 , wherein the insulating layer comprises a native oxide.

8 . The process of claim 6 , wherein patterning the dielectric layer is performed such that the opening has an aspect ratio of at least 7:1.

9 . The process of claim 6 , further comprising forming a memory cell before forming the dielectric layer, wherein:

the memory cell includes a gate electrode and a source/drain region; and

patterning the dielectric layer is performed such that the opening overlies the gate electrode or the source/drain region.

10 . A process of forming an electronic system comprising:

providing a processor and an electronic device formed by the process of claim 1 , wherein the electronic device and the processor are electrically coupled to each other; and

electrically coupling the processor and a display component to each other.

11 . A process of forming an electronic device comprising:

forming a doped semiconductor region;

forming a dielectric layer over the doped semiconductor region;

patterning the dielectric layer to define an opening extending to the doped semiconductor region;

forming an insulating layer along a bottom of the opening and over the doped semiconductor region; and

forming a first layer, wherein the first layer is formed by a physical vapor deposition technique at a first power sufficient, removing the insulating layer using first metal ions during forming the first layer, wherein the first layer includes an overhanging portion extending over the bottom of the opening.

12 . The process of claim 11 , wherein during forming the first layer, some of the first metal ions are implanted into the doped semiconductor region.

13 . The process of claim 11 , further comprising forming a second layer, wherein the second layer is formed by the physical vapor deposition technique using second metal ions and a second power sufficient to reduce a lateral dimension of the overhanging portion.

14 . The process of claim 13 , further comprising forming a third layer, wherein the third layer is formed by the physical vapor deposition technique using third metal ions and a third power, wherein the third power is between the first power and the second power.

15 . The process of claim 11 , further comprising:

forming a conductive layer, such that after forming the conductive layer, the opening is substantially filled with conductive materials; and

removing portions of the conductive layer and the first layer overlying the dielectric layer and outside the opening to form a conductive structure.

16 . A process of forming an electronic device comprising:

forming a first memory cell and a second memory cell, wherein the first memory cell and the second memory cell share a common source/drain region;

forming a dielectric layer over the first memory cell and the second memory cell;

patterning the dielectric layer to define an opening extending to the common source/drain region;

growing a native oxide from a portion of the common source/drain region;

physical vapor depositing a first layer over dielectric layer and within the opening, wherein depositing the first layer is performed using a source material and at a first alternating current (“AC”) power and using a source material;

physical vapor depositing a second layer over the first layer and within the opening, wherein depositing the second layer using the source material and is performed at a second AC power that is different from the first AC power;

physical vapor depositing a third layer over the second layer, wherein depositing the third layer is performed using the source material and at a third AC power that is between the first AC power and the second AC power;

forming a fourth layer over the third layer and within the opening, such that after forming the fourth layer, the opening is filled, wherein the fourth layer comprises a different element as compared to the first layer, the second layer, and the third layer; and

removing portions of the first layer, the second layer, the third layer, and the fourth layer to form a conductive structure.

17 . The process of claim 16 , wherein:

forming the first memory cell and the second memory cell is performed using a substrate having a nominal diameter of 200 mm;

the first AC power is in a range of approximately 700 watts to approximately 1100 watts;

the second AC power is in a range of approximately 200 watts to approximately 400 watts; and

the third AC power is in a range of approximately 500 to 900 watts.

18 . The process of claim 16 , wherein patterning the dielectric layer is performed such that the opening has an aspect ratio of at least 7:1.

19 . The process of claim 18 , wherein after depositing the third layer:

a first cumulative thickness comprises a sum of thicknesses of the first layer, the second layer, and the third layer along a bottom of the opening;

a second cumulative thickness comprises a sum of thicknesses of the first layer, the second layer, and the third layer over the dielectric layer and spaced apart from the opening; and

the first cumulative thickness divided by the second cumulative thickness is at least 0.2.

20 . The process of claim 16 , wherein physical vapor depositing the first layer comprises implanting ions comprising the source material into the common source/drain region.