IP Library Granted Patent US 7,856,570
Granted Patent B1
US 7,856,570 · App. 11/844,836 · Granted Dec 21, 2010

Method and apparatus for shaping electronic pulses

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Quick Facts
Patent No.
US 7,856,570
App. No.
11/844,836
Granted
Dec 21, 2010
Kind
B1
Abstract

A method and system for shaping an electronic pulse with a two-pulse response. An input node receives an initial electronic pulse and splits the electronic pulse into a first path and a second path. An output node combines together the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance. An Ethernet chip generates two pulses and transmits the pulses along a first path and a second path respectively. A power combiner/splitter combines together the pulses along the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance.

Claims (27)

1. A method and system for shaping an electronic pulse with a two-pulse response, comprising:

An input node for receiving an initial electronic pulse with an associated source impedance, said input node splitting the electronic pulse into a first path and a second path;

an output node for combining together the first path and the second path into an output path, and for transmitting a shaped electronic pulse;

wherein:

the first path comprises:

a first module for establishing a characteristic input impedance and introducing a first time delay;

a matched passive attenuator with substantially identical bidirectional gain,

matched to the characteristic path impedance, for reducing the amplitude of a received electronic pulse;

a first resistive element coupling the output of the matched attenuator with the second node; and,

the second path comprises:

a second module for establishing a characteristic input impedance and introducing a second time delay;

a second resistive element coupling the output of the second module with the second node.

2. The method and system of claim 1 wherein the characteristic impedance in the first path is substantially equal to twice the source impedance.

3. The method and system of claim 1 wherein the characteristic impedance in the second path is substantially equal to twice the source impedance.

4. The method and system of claim 1 wherein the ports of the matched attenuator are matched to characteristic impedance of the path.

5. The method and system of claim 1 wherein the spacing of the two-pulse response is shaped by the difference between the total time delay associated with the first path and the total time delay associated with the second path.

6. The method and system of claim 1 wherein the relative amplitudes associated with the two-pulse response are shaped by the matched attenuator.

7. The method and system of claim 1 wherein the source impedance is substantially equal to the output impedance.

8. The method and system of claim 1 wherein the source impedance is substantially equal to 50 ohms.

9. The method and system of claim 1 wherein the characteristics impedance in the first path is substantially equal to 100 ohms.

10. The method and system of claim 1 wherein the characteristic impedance in the second path is substantially equal to 100 ohms.

11. The method and system of claim 1 wherein the output impedance is substantially equal to 50 ohms.

12. The method and system of claim 1 wherein the first resistive element is substantially equal to 62 ohms.

13. The method and system of claim 1 wherein the second resistive element is substantially equal to 62 ohms.

14. The system of claim 1 further comprising: an additional passive attenuator inserted between the output node and a resistive load.

15. The system of claim 1 wherein the said passive attenuator is a static passive attenuator.

16. The system of claim 1 wherein the said passive attenuator is a dynamic, programmable passive attenuator.

Assignments (10)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
RELEASE OF SECURITY INTEREST Recorded Aug 30, 2011
From: SILICON VALLEY BANK
To: NETLOGIC MICROSYSTEMS, INC.; NETLOGIC MICROSYSTEMS INTERNATIONAL LIMITED; NETLOGIC MICROSYSTEMS CAYMANS LIMITED
Reel/Frame 026830/0141 →
SECURITY AGREEMENT Recorded Jul 17, 2009
From: NETLOGIC MICROSYSTEMS, INC.; NETLOGIC MICROSYSTEMS INTERNATIONAL LIMITED; NETLOGIC MICROSYSTEMS CAYMANS LIMITED
To: SILICON VALLEY BANK
Reel/Frame 022973/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2007
From: AELUROS, INC.
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 020174/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2007
From: AELUROS, INC.
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 020403/0192 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2007
From: LIAW, HAW-JYH; VERMA, SHWETABH
To: AELUROS, INC.
Reel/Frame 019743/0765 →