IP Library Granted Patent US 7,772,704
Granted Patent B2
US 7,772,704 · App. 11/845,473 · Granted Aug 10, 2010

Semiconductor device

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Quick Facts
Patent No.
US 7,772,704
App. No.
11/845,473
Granted
Aug 10, 2010
Kind
B2
Abstract

As a discrete semiconductor chip, there has been known one that enables flip-chip mounting by providing first and second electrodes in a current path above a first surface of a semiconductor substrate. However, there is a problem that a horizontal current flow in the substrate increases resistance components. A first electrode and a second electrode, which are connected to an element region, are provided above a first surface. Moreover, a thick metal layer having corrosion resistance and oxidation resistance and also having a low resistance is provided above a second surface. Thus, resistance components of a current flowing in a horizontal direction of a substrate are reduced. Moreover, by appropriately selecting a thickness of the thick metal layer, a resistance value of a device can be reduced while suppressing a cost increase. Furthermore, by adopting Au as the thick metal layer, defects such as discoloration of the thick metal layer with time can be prevented.

Claims (94)

1. A semiconductor device comprising:

a semiconductor substrate comprising a first surface and a second surface;

a discrete semiconductor element formed in the semiconductor substrate;

a first electrode and a second electrode that are disposed on the first surface and connected with the discrete semiconductor element;

a first metal layer formed on the second surface so as to form an uppermost layer covering the second surface; and

a second metal layer disposed between the first metal layer and the second surface of the semiconductor substrate,

wherein the semiconductor device comprises a current path configured so that a current flows from the first electrode to first and second metal layers through the semiconductor substrate, flows along the first and second metal layers, and flows from the first and second metal layers to the second electrode through the semiconductor substrate upon application of voltages to the first and second electrodes,

the first metal layer is thicker than the second metal layer, and

the first metal layer has a higher degree of corrosion resistance or oxidation resistance than the second metal layer.

2. A semiconductor device comprising:

a semiconductor substrate comprising a first surface and a second surface;

a discrete semiconductor element formed in the semiconductor substrate;

a first electrode and a second electrode that are disposed on the first surface and connected with the discrete semiconductor element;

a first metal layer formed on the second surface so as to form an uppermost layer covering the second surface;

a second metal layer disposed between the first metal layer and the second surface of the semiconductor substrate; and

a third metal layer disposed between the second metal layer and the first metal layer,

wherein the semiconductor device comprises a current path configured so that a current flows from the first electrode to first, second and third metal layers through the semiconductor substrate, flows along the first, second and third metal layers, and flows from the first, second and third metal layers to the second electrode through the semiconductor substrate upon application of voltages to the first and second electrodes,

the first metal layer is thinner than the third metal layer, and

the first metal layer has a higher degree of corrosion resistance or oxidation resistance than the third metal layer.

3. The semiconductor device of claim 1 , wherein the first metal layer comprises gold.

4. A semiconductor device comprising:

a semiconductor substrate comprising a first surface and a second surface;

a discrete semiconductor element formed in the semiconductor substrate;

a first electrode and a second electrode that are disposed on the first surface and connected with the discrete semiconductor element;

a first metal layer formed on the second surface so as to form an uppermost layer covering the second surface;

a second metal layer disposed between the first metal layer and the second surface of the semiconductor substrate; and

a third metal layer disposed between the second metal layer and the first metal layer,

wherein a current path is configured to be formed between the first and second electrodes through the semiconductor substrate and the first, second and third metal layers upon application of voltages to the first and second electrodes,

the first metal layer is thinner than the third metal layer,

the first metal layer has a higher degree of corrosion resistance or oxidation resistance than the third metal layer, and

the first metal layer comprises gold, and the third metal layer comprises copper.

5. A semiconductor device comprising:

a semiconductor substrate comprising a first surface and a second surface;

a discrete semiconductor element formed in the semiconductor substrate;

a first electrode and a second electrode that are disposed on the first surface and connected with the discrete semiconductor element;

a first metal layer formed on the second surface so as to form an uppermost layer covering the second surface; and

a second metal layer disposed between the first metal layer and the second surface of the semiconductor substrate,

wherein a current path is configured to be formed between the first and second electrodes through the semiconductor substrate and the first and second metal layers upon application of voltages to the first and second electrodes,

the first metal layer is thicker than the second metal layer,

the first metal layer has a higher degree of corrosion resistance or oxidation resistance than the second metal layer, and

a thickness of the first metal layer corresponds to a saturation limit at which a resistance against the current path is no longer significantly reduced upon increasing the thickness of the first metal layer.

6. A semiconductor device comprising:

a semiconductor substrate comprising a first surface and a second surface;

a discrete semiconductor element formed in the semiconductor substrate;

a first electrode and a second electrode that are disposed on the first surface and connected with the discrete semiconductor element;

a first metal layer formed on the second surface so as to form an uppermost layer covering the second surface;

a second metal layer disposed between the first metal layer and the second surface of the semiconductor substrate; and

a third metal layer disposed between the second metal layer and the first metal layer,

wherein a current path is configured to be formed between the first and second electrodes through the semiconductor substrate and the first, second and third metal layers upon application of voltages to the first and second electrodes,

the first metal layer is thinner than the third metal layer,

the first metal layer has a higher degree of corrosion resistance or oxidation resistance than the third metal layer, and

a thickness of the third metal layer corresponds to a saturation limit at which a resistance against the current path is no longer significantly reduced upon increasing the thickness of the third metal layer.

7. The semiconductor device of claim 1 , wherein a thickness of the first metal layer is 5000 Å to 20000 Å.

8. The semiconductor device of claim 2 , wherein a thickness of the third metal layer is 5000 Å to 20000 Å.

9. The semiconductor device of claim 1 , wherein the discrete semiconductor element comprises a field-effect transistor, a bipolar transistor or a diode.

10. The semiconductor device of claim 2 , wherein the discrete semiconductor element comprises a field-effect transistor, a bipolar transistor or a diode.

11. A semiconductor device comprising:

a semiconductor substrate comprising a first surface and a second surface;

a first discrete semiconductor element of insulating gate type formed in the semiconductor substrate;

a second discrete semiconductor element of insulating gate type formed in the semiconductor substrate;

a drain region that is part of the substrate and operates as a drain common to the first and second discrete semiconductor elements;

a first source electrode and a second source electrode that are disposed on the first surface and connected with the first and second discrete semiconductor elements, respectively;

a first metal layer formed on the second surface so as to form an uppermost layer covering the second surface; and

a second metal layer disposed between the first metal layer and the second surface of the semiconductor substrate,

wherein the semiconductor device comprises a current path configured so that a current flows from the first source electrode to first and second metal layers through the semiconductor substrate, flows along the first and second metal layers, and flows from the first and second metal layers to the second source electrode through the semiconductor substrate upon application of voltages to the first and second electrodes,

the first metal layer is thicker than the second metal layer, and

the first metal layer has a higher degree of corrosion resistance or oxidation resistance than the second metal layer.

12. A semiconductor device comprising:

a semiconductor substrate comprising a first surface and a second surface;

a first discrete semiconductor element of insulating gate type formed in the semiconductor substrate;

a second discrete semiconductor element of insulating gate type formed in the semiconductor substrate;

a drain region that is part of the substrate and operates as a drain common to the first and second discrete semiconductor elements;

a first source electrode and a second source electrode that are disposed on the first surface and connected with the first and second discrete semiconductor elements, respectively;

a first metal layer formed on the second surface so as to form an uppermost layer covering the second surface;

a second metal layer disposed between the first metal layer and the second surface of the semiconductor substrate; and

a third metal layer disposed between the second metal layer and the first metal layer,

wherein the semiconductor device comprises a current path configured so that a current flows from the first source electrode to first, second and third metal layers through the semiconductor substrate, flows along the first, second and third metal layers, and flows from the first, second and third metal layers to the second source electrode through the semiconductor substrate upon application of voltages to the first and second electrodes,

the first metal layer is thinner than the third metal layer, and

the first metal layer has a higher degree of corrosion resistance or oxidation resistance than the third metal layer.

13. The semiconductor device of claim 11 , wherein the first metal layer comprises gold.

14. A semiconductor device comprising:

a semiconductor substrate comprising a first surface and a second surface;

a first discrete semiconductor element of insulating gate type formed in the semiconductor substrate;

a second discrete semiconductor element of insulating gate type formed in the semiconductor substrate;

a drain region that is part of the substrate and operates as a drain common to the first and second discrete semiconductor elements;

a first source electrode and a second source electrode that are disposed on the first surface and connected with the first and second discrete semiconductor elements, respectively;

a first metal layer formed on the second surface so as to form an uppermost layer covering the second surface;

a second metal layer disposed between the first metal layer and the second surface of the semiconductor substrate; and

a third metal layer disposed between the second metal layer and the first metal layer,

wherein a current path is configured to be formed between the first and second source electrodes through the semiconductor substrate and the first, second and third metal layers upon application of voltages to the first and second source electrodes,

the first metal layer is thinner than the third metal layer,

the first metal layer has a higher degree of corrosion resistance or oxidation resistance than the third metal layer, and

the first metal layer comprises gold, and the third metal layer comprises copper.

15. The semiconductor device of claim 1 , wherein a voltage applied to the first electrode is different from a voltage applied to the second electrode.

Assignments (14)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2016
From: SYSTEM SOLUTIONS CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038994/0667 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2016
From: ON SEMICONDUCTOR NIIGATA CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038988/0804 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CHANGE OF NAME Recorded Aug 11, 2015
From: SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
To: ON SEMICONDUCTOR NIIGATA CO., LTD.
Reel/Frame 036327/0871 →
CHANGE OF NAME Recorded Aug 11, 2015
From: SANYO SEMICONDUCTOR CO., LTD.
To: SYSTEM SOLUTIONS CO., LTD
Reel/Frame 036300/0238 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER LISTED ON THE NAME CHANGE USP 7619299 PREVIOUSLY RECORDED ON REEL 025762, FRAME 0635 Recorded Jun 6, 2011
From: NIGATA SANYO ELECTRIC CO., LTD.
To: SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 026424/0676 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 7619299, PREVIOUSLY RECORDED ON REEL 025762 FRAME 0320.ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT Recorded Jun 2, 2011
From: SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
To: NIGATA SANYO ELECTRIC CO., LTD.
Reel/Frame 026654/0343 →
COMPANY SPLIT Recorded Dec 22, 2010
From: SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
To: NIGATA SANYO ELECTRIC CO., LTD.
Reel/Frame 025762/0320 →
CHANGE OF NAME Recorded Dec 22, 2010
From: NIGATA SANYO ELECTRIC CO., LTD.
To: SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 025762/0635 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2007
From: YOSHIDA, TETSUYA; KOBAYASHI, MITSUYUKI
To: SANYO ELECTRIC CO., LTD.; SANYO SEMICONDUCTOR CO., LTD.; SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 020148/0013 →