Semiconductor storage device
View Patent ↗Semiconductor storage device of reduced layout area having memory cell rows accessed selectively. Memory cells, each including a programmable resistive element, are connected by a bit line to form a memory cell row. Selecting circuit for selecting a memory cell row includes a first NMOS transistor having first end connected to write amplifier, second end connected to the bit line, and a gate, and controlled such that, if the write amplifier outputs a voltage level on power-supply side after the block-select activating signal has been activated, a voltage of the same polarity as that of the power-supply voltage and exceeding the voltage level of the power supply is applied to the gate. A second NMOS transistor has first end to which the block-select activating signal is applied, a gate connected to the power supply, and second end connected to the gate of the first NMOS transistor.
1. A semiconductor storage device comprising:
a plurality of memory cell rows each of which includes a plurality of memory cells provided at intersections between a bit line and a word line, memory cells in each of said memory cell rows being connected by the bit line;
a write amplifier; and
a selecting circuit that selectively connects one of said memory cell rows to said write amplifier via a bit line by a block-select activating signal;
wherein said selecting circuit includes a first MOS transistor having a first end connected to said write amplifier, a second end connected to the bit line, and a control end, so as to be controlled in such a manner that if said write amplifier outputs a voltage level on a power-supply side after the block-select activating signal has been activated, a voltage of the same polarity as that of the voltage on the power-supply side and exceeding the voltage level is applied to the control end.
2. The device according to claim 1 , wherein said selecting circuit further comprises a second MOS transistor of the same conductivity type as that of said first MOS transistor, having a first end to which the block-select activating signal is applied, a control end connected to the power-supply side, and a second end connected to the control end of the first MOS transistor.
3. The device according to claim 1 , wherein each memory cell includes a programmable resistive element.
4. The device according to claim 2 , wherein each memory cell includes a programmable resistive element.
5. The device according to claim 3 , wherein said programmable resistive element is a phase-change element.
6. The device according to claim 4 , wherein said programmable resistive element is a phase-change element.
7. The device according to claim 3 , wherein said programmable resistive element is a tunnel magnetoresistive element
8. The device according to claim 4 , wherein said programmable resistive element is a tunnel magnetoresistive element.
9. The device according to claim 2 , wherein said second MOS transistor has a substantially smaller gate size than that of the first MOS transistor.
10. The device according to claim 4 , wherein said second MOS transistor has a gate extending in a direction transverse to that of the gate of the first MOS transistor.
11. The device according to claim 2 , wherein said control end of said second MOS transistor comprises a gate which is formed as a part of a power supply line per se.
12. A semiconductor storage device comprising:
a plurality of memory cell rows each of which includes a plurality of memory cells provided at intersections between a bit line and a word line, memory cells in each of said memory cell rows being connected by the bit line;
a write amplifier; and
a selecting circuit that selectively connects one of said memory cell rows to said write amplifier via a bit line by a block-select activating signal;
wherein said selecting circuit includes a first MOS transistor and a second MOS transistor having the same conductivity type,
said first MOS transistor having a first end connected to said write amplifier, a second end connected to the bit line, and a control gate;
said second MOS transistor having a first end to which the block-select activating signal is applied, a control end connected to the power-supply side, and a second end connected to the control gate of the first MOS transistor.
13. The device according to claim 12 , wherein said second MOS transistor has a substantially smaller gate size than that of the first MOS transistor.
14. The device according to claim 12 , wherein said control gate of the second MOS transistor extends in a direction transverse to that of said control gate of the first MOS transistor.
15. The device according to claim 12 , wherein said control gate of the second MOS transistor is formed as a part of a power supply line per se.
16. The device according to claim 12 , wherein said selecting circuit is controlled in such a manner that if said write amplifier outputs a voltage level on a power-supply side after the block-select activating signal has been activated, a voltage of the same polarity as that of the voltage on the power-supply side and exceeding the voltage level is applied to the control gate of said first MOS transistor.
17. A semiconductor storage device comprising:
a plurality of memory cell rows each of which includes a plurality of memory cells provided at intersections between a bit line and a word line, memory cells in each of said memory cell rows being connected by the bit line;
a write amplifier; and
a selecting circuit that selectively connects one of said memory cell rows to said write amplifier via a bit line by a block-select activating signal;
wherein said selecting circuit includes first and second MOS transistors having the same conductivity type;
said first MOS transistor having a first end connected to said write amplifier, a second end connected to the bit line, and a control gate;
said second MOS transistor having a first end to which the block-select activating signal is applied, a control gate connected to the power-supply side, and a second end connected to the control gate of the first MOS transistor;
said control gate of the second MOS transistor being substantially smaller in size that of the first MOS transistor.
18. The device according to claim 17 , wherein said control gate of the second MOS transistor extends in a direction transverse to that of the control gate of the first MOS transistor.
19. The device according to claim 18 , wherein said control gate of the second MOS transistor is formed as a part of a power supply line per se.