Sacrificial nitride and gate replacement
Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.
1. A method of forming top oxides of memory cells, comprising:
forming dielectric layers on a semiconductor substrate, forming sacrificial nitride layers only over the dielectric layers, and forming first poly layers over the nitride layers;
removing end portions of the dielectric layers thereby forming openings between the sacrificial nitride layers and the semiconductor substrate and exposing portions of bottom surfaces of the sacrificial nitride layers in the openings;
oxidizing the exposed bottom surfaces of the sacrificial nitride layers to form top oxides; and
then forming charge storage material layers in the openings.
2. The method of claim 1 further comprising forming bit line dielectrics in bit line openings on the semiconductor substrate between the first poly layers.
3. The method of claim 1 further comprising forming a second poly layer over the semiconductor substrate.
4. The method of claim 1 , wherein oxidizing the at least portions of the nitride layers comprises a slot plane antenna process.
5. The method of claim 1 , wherein the nitride layers comprise silicon nitrides.
6. The method of claim 1 , wherein the memory cell comprises two charge storage nodes that are separated from each other by the dielectric layers.
7. The method of claim 1 , wherein the two charge storage nodes comprise a ORPRO layer.
8. The method of claim 1 further comprising entirely oxidizing the nitride layers to convert the nitride layers into top oxide layers.
9. The method of claim 1 further comprising:
oxidizing exposed portions or the dielectric layers and the semiconductor substrate in the openings.
10. A method of improving quality of a top oxide of a memory cell, comprising:
providing a charge storage layer on a semiconductor substrate, providing a sacrificial nitride layer, and providing a first poly layer on the sacrificial nitride layer, and converting the sacrificial nitride layer to a top oxide, wherein providing the charge storage layer comprises:
forming a dielectric layer on the semiconductor, forming a sacrificial nitride layer only on the dielectric layer, removing end portions of the dielectric layer and forming openings between the sacrificial nitride layer and the semiconductor substrate, and then forming a charge storage material layer in the opening; and
wherein converting the sacrificial nitride layer to a top oxide comprises:
forming openings under the sacrificial nitride layer on the semiconductor substrate to expose portions of a bottom surface of the sacrificial nitride layer; and oxidizing the exposed portions of the bottom surface of the sacrificial nitride layer.
11. The method of claim 10 , wherein converting the nitride layer to a top oxide comprises:
removing the first poly layer to expose an upper portions of the nitride layer; and
oxidizing the exposed portions of the upper surface of the nitride layer.
12. The method of claim 10 further comprising forming bit line dielectrics in bit line openings between the first poly layers.
13. The method of claim 10 further comprising forming a second poly layer or a word line over the semiconductor substrate.
14. The method of claim 10 , wherein converting the nitride layer comprises a slot plane antenna process.
15. A method of forming top oxides of memory cells, comprising:
forming dielectric layers on a semiconductor substrate, forming sacrificial nitride layers only over the dielectric layers, and forming first poly layers over the sacrificial nitride layers;
removing end portions of the dielectric layers thereby forming openings between the sacrificial nitride layers and the semiconductor substrate and exposing portions of bottom surfaces of the sacrificial nitride layers, portions of the dielectric layers and portions of the semiconductor substrate in the openings;
forming an oxide layer over the exposed portions of the bottom surfaces of the sacrificial nitride layers, the exposed portions of the dielectric layers, and the exposed portions of the semiconductor substrate in the openings; and
then forming charge storage material layers in the openings.
16. The method of claim 15 , wherein the forming the oxide layer includes oxidizing the exposed portions of the bottom surfaces of the nitride layers, the exposed portions of the dielectric layers, and the exposed portions of the semiconductor substrate in the openings.
17. The method of claim 15 , wherein the forming the oxide layer includes depositing oxide materials on the exposed portions of the bottom surfaces of the nitride layers, the exposed portions of the dielectric layers, and the exposed portions of the semiconductor substrate in the openings.
18. The method of claim 15 , wherein the forming the oxide layer over the exposed portions of the bottom surfaces of the nitride layers includes entirely oxidizing the nitride layers to convert the nitride layers into top oxide layers.