Voltage regulator for integrated circuits
View Patent ↗A voltage regulator for a charge pump includes a capacitor divider and a reset circuit. The capacitor divider produces, based on an input voltage (VPP), a sample voltage at a sampling node. The sampling node and a reference voltage VREF are connected to respective inputs of a comparator that generates an enable signal for the charge pump. The reset circuit connects to the divider and includes a first transistor connected between the sampling node and a biasing node. During a sampling mode, the reset circuit biases VDS of the first transistor to approximately zero at the regulation point to minimize sub-threshold IDS. During reset intervals, the reset circuit applies VREF to the biasing node. The reset circuit may include a second transistor connected between the biasing node and a known level (e.g., ground) and a biasing transistor connected between the biasing node and VREF.
1. A voltage regulator operable in a reset mode and a sampling mode, the voltage regulator comprising:
a capacitor divider operable in the sampling mode to generate, at a sampling node, a sample voltage (VSAMPLE) from a voltage to be regulated (VPP) wherein VSAMPLE is indicative of VPP;
a reset circuit including a first reset transistor connected to the sampling node and operable to:
discharge a first capacitor of the capacitor divider through the first reset transistor in the reset mode; and
bias, in the sampling mode, the first reset transistor wherein a voltage across current terminals of the first reset transistor is approximately 0 V; and
a comparison circuit operable in the sampling mode to compare VSAMPLE to a reference voltage VREF and generate an enable signal based thereon.
2. The voltage regulator of claim 1 , wherein a control terminal of the first reset transistor is configured to receive a reset signal (RESET) that is asserted during the reset mode, wherein the first transistor conducts during the reset mode and does not conduct during the sampling mode.
3. The voltage regulator of claim 1 , wherein a first current terminal of the first reset transistor is connected to the sampling node and a second current terminal of the first reset transistor is connected to a biasing node.
4. The voltage regulator of claim 3 , further comprising a second reset transistor having a first current terminal connected to the biasing node and a second current terminal connected to ground, wherein a control terminal of the second reset transistor is configured to receive the reset signal RESET, wherein the second reset transistor is conductive during the reset mode and is not conductive during the sampling mode.
5. The voltage regulator of claim 4 , wherein the capacitor divider includes the first capacitor connected between ground and the sampling node and a second capacitor connected between the sampling node and an upper node.
6. The voltage regulator of claim 5 , further comprising a switch transistor having current terminals connected between the upper node and VPP wherein the switch transistor is operable to be conductive during the sampling mode and to be not conductive during the reset mode.
7. The voltage regulator of claim 1 , further comprising a third reset transistor having a first current terminal connected to the upper node and a second current terminal connected to ground, wherein a control electrode of the third reset transistor is configured to receive the reset signal RESET, wherein the third reset transistor is ON during the reset mode and OFF during the sampling mode.
8. The voltage regulator of claim 7 , wherein the first, second, and third reset transistors and the biasing transistor are NMOS transistors and the switch transistor is an PMOS transistor.
9. The voltage regulator of claim 3 , wherein the reset circuit is operable to bias the biasing node to VREF during the sampling mode.
10. The voltage regulator of claim 9 , further comprising a biasing transistor having current terminals connected between the biasing node and VREF, wherein a control electrode of the biasing transistor is configured to receive an inverted RESET signal wherein the biasing transistor is OFF during reset mode and ON during sampling mode.
11. A circuit, comprising:
a charge pump operable to receive a supply voltage (VCC) and produce a programming voltage (VPP) that is different than VCC; and
a voltage regulator configured to receive VPP as a first input signal and a reference voltage (VREF) as a second input signal and operable to generate, during a sampling mode, an enable signal based on VPP and VREF, wherein the enable signal activates the charge pump;
wherein the voltage regulator is operable in the sampling mode and in a reset mode and includes:
a capacitive circuit including a first capacitor, wherein the capacitive circuit is operable in the sampling mode to produce a sample voltage (VSAMPLE) at a sampling node wherein VSAMPLE is indicative of VPP;
a comparator to compare VSAMPLE to VREF to produce the enable signal; and
a first reset transistor connected between the sampling node and a biasing node; and
wherein the voltage regulator is operable to:
discharge, through the first transistor, the first capacitor during the reset mode; and
turn off the first transistor and bias the biasing node to VREF during the sampling mode.
12. The circuit of claim 11 , wherein the first reset transistor, the first capacitor, a second capacitor of the capacitor divider, and a first input of the comparator are each connected to the sampling node.
13. The circuit of claim 11 , wherein the capacitive circuit includes the first capacitor connected between ground and the sampling node and a second capacitor connected between the sampling node and an upper node and further wherein the voltage regulator is further operable to discharge the second capacitor in the reset mode wherein the sampling node and the upper node are reset to a known level prior to termination of the sampling mode.
14. The circuit of claim 11 , further comprising:
a second reset transistor having current terminals connected between ground and the biasing node; and
a biasing transistor having current terminals connected between VREF and the biasing node;
wherein the first and second reset transistor are operable to be conductive during the reset mode and not conductive during the sampling mode and the biasing transistor is operable to be non conductive during the reset mode and conductive during the sampling mode.
15. The circuit of claim 14 , further comprising:
a switch transistor connected between VPP and the upper node; and
a third reset transistor connected between the upper node and ground;
wherein the switch transistor is operable to be not conductive during the reset mode and conductive during the sampling mode and the third reset transistor is operable to be conductive during the reset mode and non conductive during the sampling mode.
16. The circuit of claim 11 , wherein the first reset transistor is an NMOS transistor.
17. A voltage regulator operable in sampling mode and a reset mode, the voltage regulator comprising a capacitor divider operable to produce from an input voltage (VPP) a divided down voltage at a sampling node during the sampling mode, wherein a primary leakage path from the sampling node comprises a first reset transistor having its current terminals connected between the sampling node and a biasing node, wherein the first reset transistor is operable to be OFF in the sampling mode and further wherein the biasing node is biased, in the sampling mode, to a reference voltage (VREF) that is approximately equal to the divided down voltage.
18. The voltage regulator of claim 17 , further comprising a comparator configured to receive the divided down voltage as a first input, VREF as a second input and operable, in the sampling mode, to produce an enable signal indicative of the relative magnitudes of the divided down voltage and VREF.
19. The voltage regulator of claim 17 , wherein the primary leakage path further comprises a second reset transistor having its current terminals connected between the biasing node and ground wherein the second reset transistor is operable to be ON during the reset mode and OFF during the sampling mode.
20. The voltage regulator of claim 17 , further comprising a biasing transistor having its current terminals connected between the biasing node and VREF wherein the biasing transistor is operable to be OFF during the reset mode and ON during the sampling mode.
21. The voltage regulator of claim 17 , wherein the capacitor divider includes a first capacitor connected between ground and the sampling node and a second capacitor connected between the sampling node and an upper node wherein the voltage regulator is configured to discharge the first and second capacitors in the reset mode.
22. The voltage regulator of claim 17 , wherein the first reset transistor is an NMOS transistor.