Statistical design closure
A method of statistical design closure is disclosed. The method generally includes the steps of (A) reading statistical data from a database, the statistical data defining a plurality of chip yield improvements, one of the chip yield improvements in each one of a plurality of design closure categories respectively, the chip yield improvements capturing historically trends based on a plurality of previous projects, (B) calculating a plurality of targets of a current design closure project based on the statistical data, one of the targets in each one of the design closure categories respectively and (C) generating a resource report to a user that indicates a plurality of resources expected to be used the current design closure project.
1. A method of statistical design closure, comprising the steps of:
(A) reading statistical data from a database, said statistical data defining a plurality of chip yield improvements, one of said chip yield improvements in each one of a plurality of design closure categories respectively;
(B) generating a plurality of targets of a current design closure project suitable to achieve an expected chip yield, said generating of said targets is based on said statistical data and is performed by a computer, one of said targets is defined in each one of said design closure categories respectively, said targets comprising respective percentages of a plurality of goals of said current design closure project to be finished; and
(C) generating a resource report to a user that indicates a plurality of resources expected to be used by said current design closure project.
2. The method according to claim 1 , further comprising the step of:
receiving said goals of said current design closure project from said user, wherein at least one of said goals is defined in each of said design closure categories.
3. The method according to claim 1 , wherein said targets in each of at least two of said design closure categories comprise less than 100 percent of said goals in said at least two design closure categories.
4. The method according to claim 1 , wherein said goals comprise (i) a power consumption goal, (ii) a timing goal, (iii) a routing goal, (iv) an area goal, (v) a headcount goal and (vi) a turn-around-time goal.
5. The method according to claim 1 , further comprising the step of:
receiving said expected chip yield from said user.
6. The method according to claim 1 , further comprising the step of:
generating a yield report to said user indicating if said targets will meet said expected chip yield.
7. The method according to claim 6 , further comprising the step of:
receiving an adjustment to said expected chip yield from said user in response to said yield report indicating that said targets will not meet said expected chip yield.
8. The method according to claim 1 , further comprising the step of:
performing said current design closure project, wherein each of said design closure categories is finished upon achieving said targets respectively.
9. The method according to claim 1 , wherein said design closure categories comprise (i) synthesis, (ii) placement, (iii) routing, (iv) timing, (v) power, (vi) area, (vii) headcount and (viii) turn-around-time.
10. The method according to claim 1 , further comprising a storage medium recording a computer program comprising the steps of claim 1 .
11. A method of statistical design closure, comprising the steps of:
(A) reading statistical data from a database, said statistical data defining a plurality of chip yield improvements, one of said chip yield improvements in each one of a plurality of design closure categories respectively;
(B) receiving an expected chip yield from a user;
(C) generating a plurality of targets of a current design closure project suitable to achieve said expected chip yield, said generating of said targets is based on said statistical data and is performed by a computer, one of said targets is defined in each one of said design closure categories respectively, said targets comprising respective percentages of a plurality of goals of said current design closure project to be finished; and
(D) generating a yield report to said user indicating if said targets will meet said expected chip yield.
12. The method according to claim 11 , further comprising the step of:
receiving said goals of said current design closure project from said user, wherein at least one of said goals is defined in each of said design closure categories.
13. The method according to claim 11 , wherein said targets in each of at least two of said design closure categories comprise less than 100 percent of said goals in said at least two design closure categories.
14. The method according to claim 11 , wherein said goals comprise (i) a power consumption goal, (ii) a timing goal, (iii) a routing goal, (iv) an area goal, (v) a headcount goal and (vi) a turn-around-time goal.
15. The method according to claim 11 , further comprising the step of:
receiving an adjustment to said expected chip yield from said user in response to said yield report indicating that said targets will not meet said expected chip yield.
16. The method according to claim 11 , further comprising the step of:
generating a resource report to said user that indicates a plurality of resources expected to be used by said current design closure project.
17. The method according to claim 16 , wherein said resources comprise staffing of said current design closure project.
18. The method according to claim 11 , further comprising the step of:
performing said current design closure project, wherein each of said design closure categories is finished upon achieving said targets associated with said design closure categories respectively.
19. The method according to claim 11 , wherein said design closure categories comprise (i) synthesis, (ii) placement, (iii) routing, (iv) timing, (v) power, (vi) area, (vii) headcount and (viii) turn-around-time.
20. The method according to claim 11 , further comprising a storage medium recording a computer program comprising the steps of claim 11 .