IP Library Granted Patent US 7,671,360
Granted Patent B2
US 7,671,360 · App. 11/849,522 · Granted Mar 2, 2010

Semiconductor device and method of producing the same

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Quick Facts
Patent No.
US 7,671,360
App. No.
11/849,522
Granted
Mar 2, 2010
Kind
B2
Abstract

A phase change memory includes a sidewall insulation film and a heater electrode which are formed in a contact hole formed in an interlayer insulation film on a lower electrode. The heater electrode has a recessed structure. In a recessed area surrounded by the sidewall insulation film, the heater electrode and a phase change film are contacted with each other. A phase change region is formed only in an area contacted with the sidewall insulation film. The sidewall insulation film is an anti-oxidizing insulation film. The phase change region and the heater electrode which are heated to a high temperature upon rewriting are not contacted with the interlayer insulation film as an oxidizing insulation film.

Claims (55)

1. A semiconductor device comprising a lower electrode formed on a semiconductor substrate, an interlayer insulation film formed over the semiconductor substrate and the lower electrode, the interlayer insulation film including a contact hole to expose a part of the lower electrode, a sidewall insulation film formed on a sidewall of the contact hole formed in the interlayer insulation film, a heater electrode formed in the contact hole and located inside the sidewall insulation film such that an upper surface of the heater electrode is lower in level than a top end of the sidewall insulation film, a phase change film formed in contact with the interlayer insulation film, the sidewall insulation film and the part of the heater electrode, and an upper electrode formed on the phase change film, the sidewall insulation film comprising an anti-oxidization insulation film, and the phase change film being in direct contact with the sidewall insulation film without an intervention of an oxide layer.

2. The semiconductor device as claimed in claim 1 , wherein the phase change film has a phase change region which is formed on the upper surfaces of the heater electrode and the sidewall insulation film and which is not formed on an upper surface of the interlayer insulation film.

3. The semiconductor device as claimed in claim 1 , wherein the phase change film has a phase change region which is formed on the upper surfaces of the heater electrode and the sidewall insulation film and which is not formed on the upper surface of the interlayer insulation film.

4. A semiconductor device comprising:

a lower electrode formed on a semiconductor substrate;

an interlayer insulation film formed on the semiconductor substrate to cover the lower electrode;

a sidewall insulation film formed on a sidewall of a contact hole formed in the interlayer insulation film to expose the lower electrode;

a heater electrode formed in the contact hole and located inside the sidewall insulation film;

a phase change film formed in contact with upper surfaces of the interlayer insulation film, the sidewall insulation film, and the heater electrode; and

an upper electrode formed on an upper surface of the phase change film;

wherein the sidewall insulation film comprising an anti-oxidization insulation film,

the upper surfaces of the sidewall insulation film and the interlayer insulation film are planarized to be located at a same level, the upper surface of the heater electrode being lower in level than those of the interlayer insulation film and the sidewall insulation film, and

wherein the sidewall insulation film has a thickness not smaller than 5 nm and not greater than 100 nm, the semiconductor device being designed to satisfy:

50 nm≦ D+T≦ 200 nm,

where D represents a difference in level between the upper surface of the heater electrode and the upper surfaces of the interlayer insulation film and the sidewall insulation film and T represents the thickness of the sidewall insulation film.

5. The semiconductor device as claimed in claim 4 , wherein the phase change film contains at least two elements selected from germanium (Ge), antimony (Sb), tellurium (Te), selenium (Se), gallium (Ga), and indium (In).

6. The semiconductor device as claimed in claim 4 , wherein the sidewall insulation film comprises a nitride film.

7. The semiconductor device as claimed in claim 4 , further comprising a buried insulation film formed in the contact hole and located inside the heater electrode.

8. The semiconductor device as claimed in claim 1 , wherein the interlayer insulation film is a multilayer insulation film comprising an oxidizing insulation film and an anti-oxidizing insulation film.

9. A method of producing a semiconductor device, comprising:

depositing an interlayer insulation film to cover a lower electrode formed on a semiconductor substrate;

forming a contact hole in the interlayer insulation film to expose the lower electrode;

forming an anti-oxidizing sidewall insulation film on a sidewall of the contact hole;

forming a heater electrode in the contact hole and inside the sidewall insulation film;

planarizing upper surfaces of the sidewall insulation film, the heater electrode, and the interlayer insulation film so that the upper surfaces of the sidewall insulation film and the heater electrode formed inside the contact hole are located at a same level as that of the interlayer insulation film;

etching the heater electrode so that the upper surface of the heater electrode is lower in level than those of the interlayer insulation film and the sidewall insulation film;

forming a phase change film in contact with the upper surfaces of the interlayer insulation film, the side wall insulation film, and the heater electrode; and

forming an upper electrode on an upper surface of the phase change film,

wherein the sidewall insulation film has a thickness not smaller than 5 nm and not greater than 100 nm, the semiconductor device being designed to satisfy:

50 nm≦ D+T≦ 200 nm,

where D represents a difference in level between the upper surface of the heater electrode and the upper surfaces of the interlayer insulation film and the sidewall insulation film and T represents the thickness of the sidewall insulation film.

10. A method of producing a semiconductor device, comprising:

depositing an interlayer insulation film to cover a lower electrode formed on a semiconductor substrate;

forming a contact hole in the interlayer insulation film to expose the lower electrode;

forming an anti-oxidizing sidewall insulation film on a sidewall of the contact hole;

forming a heater electrode in the contact hole and inside the sidewall insulation film;

planarizing upper surfaces of the sidewall insulation film, the heater electrode, and the interlayer insulation film so that the upper surfaces of the sidewall insulation film and the heater electrode formed inside the contact hole are located at a same level as that of the interlayer insulation film;

etching the heater electrode so that the upper surface of the heater electrode is lower in level than those of the interlayer insulation film and the sidewall insulation film;

forming a phase change film in contact with the upper surfaces of the interlayer insulation film, the side wall insulation film, and the heater electrode; and

forming an upper electrode on an upper surface of the phase change film,

wherein the step of forming the heater electrode is followed by the step of forming an anti-oxidizing buried insulation film in the contact hole and inside the heater electrode.

11. The method according to claim 9 , wherein the phase change film contains at least two elements selected from germanium (Ge), antimony (Sb), tellurium (Te), selenium (Se), gallium (Ga), and indium (In).

12. The method according to claim 9 , wherein the sidewall insulation film comprises a nitride film.

13. The method according to claim 9 , wherein the interlayer insulation film is formed as a multilayer insulation film comprising an oxidizing insulation film and an anti-oxidizing insulation film.

14. A semiconductor device comprising:

a lower electrode formed on a semiconductor substrate;

an interlayer insulation film formed over the semiconductor substrate and the lower electrode, the interlayer insulation film having a contact hole to expose a part of the lower electrode;

a sidewall insulation film formed on a sidewall of the contact hole formed in the interlayer insulation film;

a heater electrode formed in the contact hole and located inside the sidewall insulation film;

a phase change film formed on upper surfaces of the interlayer insulation film, the sidewall insulation film, and the heater electrode; and

an upper electrode formed on an upper surface of the phase change film;

wherein the sidewall insulation film comprising an anti-oxidization insulation film, and

the sidewall insulation film has a thickness not smaller than 5 nm and not greater than 100 nm to satisfy:

50 nm≦ B+T≦ 200 nm,

where D represents a difference in level between the upper surface of the heater electrode and the upper surfaces of the interlayer insulation film and the sidewall insulation film and T represents the thickness of the sidewall insulation film.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2007
From: SATO, NATSUKI; HAYAKAWA, TSUTOMU
To: ELPIDA MEMORY, INC.
Reel/Frame 019778/0070 →