Semiconductor package and multi-chip semiconductor package using the same
Disclosed is a semiconductor package and a multi-chip semiconductor package. The semiconductor package includes a semiconductor chip having bonding pads located at a center portion thereof; redistribution patterns extending from the bonding pads toward one edge of the semiconductor chip; and dummy bump pads located adjacent to another edge of the semiconductor chip which is opposite the one edge.
1. A semiconductor package comprising:
a semiconductor chip having bonding pads located at a center portion thereof on a first surface of the semiconductor chip;
a plurality of redistribution patterns extending from the bonding pads towards a first edge of the semiconductor chip and having bump pads disposed along the first edge of the semiconductor chip; and
dummy bump pads disposed along a second edge of the semiconductor chip opposite the first edge,
wherein pads disposed along the second edge of the semiconductor chip comprise only dummy bump pads, and pads disposed along the first edge of the semiconductor chip comprise only bump pads.
2. The semiconductor package according to claim 1 , wherein the redistribution patterns have the shape of a line when viewed from the top, and the dummy bump pads have the shape of an island when viewed from the top.
3. The semiconductor package according to claim 1 , wherein a first insulation layer pattern is interposed between the semiconductor chip and the redistribution patterns in such a way as to expose the bonding pads.
4. The semiconductor package according to claim 3 , wherein a second insulation layer pattern is located on the first insulation layer pattern and exposes the dummy bump pads and ends of the redistribution patterns to define bump pads.
5. The semiconductor package according to claim 4 , wherein a plurality of conductive balls are selectively connected to the bump pads.
6. The semiconductor package according to claim 4 , wherein a plurality of conductive balls are connected to the dummy bump pads and the bump pads.
7. The semiconductor package according to claim 4 , wherein the dummy bump pads and the bump pads are located to be symmetrical with respect to the bonding pads.
8. The semiconductor package according to claim 1 , wherein an adhesive member is located on a second surface of the semiconductor chip which faces opposite the first surface of the semiconductor chip on which the bonding pads are formed.
9. A multi-chip semiconductor package comprising:
first, second and third semiconductor packages each including a semiconductor chip having bonding pads located at a center portion thereof, redistribution patterns extending from the bonding pads towards a first edge of the semiconductor chip and having bump pads on ends thereof, and dummy bump pads located adjacent to a second edge of the semiconductor chip opposite the first edge;
a substrate having a plurality of first connection pads which are electrically connected with the bump pads and the first connection pads which are physically connected with the dummy bump pads of the first semiconductor package;
a first connection substrate electrically connecting the bump pads of the second semiconductor package located on the first semiconductor package with second connection pads of the substrate; and
a second connection substrate electrically connecting the bump pads of the third semiconductor package located on the second semiconductor package with third connection pads of the substrate.
10. The multi-chip semiconductor package according to claim 9 , wherein adhesive members are respectively interposed between the first through third semiconductor packages.
11. The multi-chip semiconductor package according to claim 9 , wherein the bump pads and the first connection pads of the substrate are electrically connected with each other by way of conductive balls, and the dummy bump pads and the first connection pads are physically connected with each other by way of conductive balls.
12. The multi-chip semiconductor package according to claim 9 , wherein the first connection substrate comprises:
an insulation body having an upper surface and a lower surface;
a plurality of connection wirings for electrically connecting the upper and lower surfaces of the insulation body; and
a plurality of conductive balls connected to at least one of upper and lower surfaces of the respective connection wirings.
13. The multi-chip semiconductor package according to claim 9 , wherein the second connection substrate comprises:
an insulation body having an upper surface and a lower surface;
a plurality of connection wirings for electrically connecting the upper and lower surfaces of the insulation body; and
a plurality of conductive balls connected to at least one of upper and lower surfaces of the respective connection wirings.
14. The multi-chip semiconductor package according to claim 13 , wherein the thickness of the second connection substrate is greater than that of the first connection substrate.
15. The multi-chip semiconductor package according to claim 13 , wherein the thickness of the second connection substrate is the same as that of the first connection substrate, and at least two connection substrates are stacked between the substrate and the third semiconductor package.
16. The multi-chip semiconductor package according to claim 9 , wherein the second and third semiconductor packages are located on the first semiconductor package in a zigzag type such that the bump pads of the second and third semiconductor packages are exposed beyond the first semiconductor package.